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www.ti.com SLAS412− DECEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
www.ti.com SLAS412− DECEMBER 2003 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1)(2) UNITS AVDD to AVSS −0.3 V to 3.9 V DRVDD to DRVSS −0.3 V to 3.9 V IOVDD to DVSS −0.3 V to 3.9 V DVDD to DVSS −0.3 V to 2.5 V AVDD to DRVDD −0.1 V to 0.1 V AVSS to DRVSS to DVSS −0.1 V to 0.1 V Analog inputs (except VBAT1 and VBAT2) to AVSS VBAT1 / VBAT2 to AVSS −0.3 V to AVDD + 0.3 V −0.3 V to 6 V Digital input voltage to DVSS −0.3 V to IOVDD + 0.
www.ti.com SLAS412− DECEMBER 2003 ELECTRICAL CHARACTERISTICS At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BATTERY MONITOR INPUTS Input voltage range 0.5 Input leakage current 6.
www.ti.com SLAS412− DECEMBER 2003 ELECTRICAL CHARACTERISTICS At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DAC INTERPOLATION FILTER Pass band 20 0.45 Fs ±0.06 Pass band ripple Transition band Stop band Hz dB 0.45 Fs 0.5501 Fs Hz 0.5501 Fs 7.455 Fs Hz Stop band attenuation Filter group delay De−emphasis error 65 dB 21/Fs sec ±0.
www.ti.com SLAS412− DECEMBER 2003 ELECTRICAL CHARACTERISTICS At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VOLTAGE REFERENCE Voltage range VREF output programmed as 2.5 V 2.3 2.5 2.7 VREF output programmed as 1.25 V 1.15 1.25 1.35 Voltage range External VREF. By design, not tested in production. Reference drift Internal VREF = 1.
www.ti.com SLAS412− DECEMBER 2003 FUNCTIONAL BLOCK DIAGRAM DRVDD DRVSS AVDD AVSS DVDD DVSS 0 to −63.5 dB (0.5 dB Steps) Headphone Driver HPR IOVDD Σ ∑−∆ DAC Σ ∑−∆ DAC Σ Vol Ctl Σ Vol Ctl PLL MCLK PWD/ADWS Headphone Driver HPL VGND DAC CM MICBIAS 2.5 V/2 V Analog Volume Control −34.5 to 12 dB Sidetone −48 to 0 dB 1.5 dB Steps DOUT LRCK Digital Audio Processing and Serial Interface DIN BCLK 0 to 59.5 dB (0.
www.ti.com SLAS412− DECEMBER 2003 SPI TIMING DIAGRAM SS t t t Lead t Lag td s ck SCLK t wsck tf tr t wsck tv MISO t ho MSB OUT t dis BIT . . . 1 LSB OUT ta MOSI t hi t su MSB OUT BIT . . . 1 LSB OUT TYPICAL TIMING REQUIREMENTS All specifications at 25°C, DVDD = 1.8 V (1) IOVDD = 1.1 V PARAMETER MIN MAX IOVDD = 3.
www.ti.com SLAS412− DECEMBER 2003 AUDIO INTERFACE TIMING DIAGRAMS LRCK/ADWS td (WS) BCLK td (DO−WS) td (DO−BCLK) DOUT ts (DI) th (DI) DIN Figure 1. I2S/LJF/RJF Timing in Master Mode TYPICAL TIMING REQUIREMENTS (FIGURE 1) All specifications at 25°C, DVDD = 1.8 V (1) IOVDD = 1.1 V PARAMETER MIN MAX IOVDD = 3.
www.ti.com SLAS412− DECEMBER 2003 LRCK/ADWS th (WS) BCLK tL(BCLK) tS (WS) tH(BCLK) td(DO−WS) tP(BCLK) td(DO−BCLK) DOUT th (DI) ts (DI) DIN Figure 3. I2S/LJF/RJF Timing in Slave Mode TYPICAL TIMING REQUIREMENTS (FIGURE 3) All specifications at 25°C, DVDD = 1.8 V (1) IOVDD = 1.1 V PARAMETER MIN MAX IOVDD = 3.
www.ti.com SLAS412− DECEMBER 2003 LRCK/ADWS tS (WS) tH(BCLK) th(WS) th(WS) tS (WS) tL(BCLK) BCLK td(DO−BCLK) tP(BCLK) DOUT th (DI) ts (DI) DIN Figure 4. DSP Timing in Slave Mode TYPICAL TIMING REQUIREMENTS (FIGURE 4) All specifications at 25°C, DVDD = 1.8 V (1) IOVDD = 1.1 V PARAMETER MIN MAX IOVDD = 3.
www.ti.com SLAS412− DECEMBER 2003 TYPICAL CHARACTERISTICS 1.5 1 LSB 0.5 0 −0.5 −1 −1.5 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 Figure 5. SAR INL (TA = 25°C, Internal Ref = 2.5 V, 12 bit, AVDD = 3.3 V) 1 LSB 0.5 0 s −0.5 −1 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 Figure 6. SAR DNL (TA = 25°C, Internal Ref = 2.5 V, AVDD = 3.3 V) 0 −20 −40 dB −60 −80 −100 −120 −140 −160 0 500 1000 1500 2000 2500 3000 3500 4000 Hz Figure 7.
www.ti.com SLAS412− DECEMBER 2003 0 −20 −40 dB −60 −80 −100 −120 −140 −160 0 5000 10000 15000 20000 Hz Figure 8. ADC FFT Plot at 48 ksps (TA = 25°C, −1 dB, 1 kHz Input, AVDD = 3.3 V) 90 89.5 Dynamic Range − dB 89 88.5 88 87.5 87 86.5 86 8 18 28 38 Sampling Rate − ksps 48 Figure 9. ADC Dynamic Range vs Sampling Speed (TA = 25°C, AVDD = 3.3 V) 0 −20 −40 dB −60 −80 −100 −120 −140 −160 0 5000 10000 15000 20000 Hz Figure 10.
www.ti.com SLAS412− DECEMBER 2003 0 −10 −30 dB −50 −70 −90 −110 −130 −150 0 5000 10000 Hz 15000 20000 Figure 11. DAC FFT Plot (TA = 25°C, 48 ksps, −1 dB, 1 kHz Input, AVDD = DRVDD = 3.3 V, DVDD = 1.8 V, RL = 16 Ω) THD − Total Harmonic Distortion − dB −88 −90 −92 −94 5 15 25 35 Output Power − mW Figure 12. High Power Output Driver THD vs Output Power (TA =25°C, AVDD, DRVDD = 3.
www.ti.com SLAS412− DECEMBER 2003 OVERVIEW The ’AIC26 is a highly integrated stereo audio codec for portable computing, communication, and entertainment applications. The ’AIC26 has a register-based architecture where all functions are controlled through the registers and onboard state machines.
www.ti.com SLAS412− DECEMBER 2003 OPERATION−AUDIO CODEC Audio Analog I/O The ’AIC26 has one mono audio input (MICIN) typically used for microphone recording, and an auxiliary input (AUX) that can be used as a second microphone or line input. The dual audio output drivers have programmable power level and can be configured to drive up to 325 mW into an 8-Ω speaker, or to drive 16-Ω stereo headphones at over 30-mW per channel, or to provide a stereo line-level output.
www.ti.com SLAS412− DECEMBER 2003 D RIGHT-JUSTIFIED MODE In right-justified mode, the LSB of the left channel is valid on the rising edge of the BCLK preceding the falling edge of ADWS or LRCK. Similarly, the LSB of the right channel is valid on the rising edge of the BCLK preceding the rising edge of ADWS or LRCK. 1/fs ADWS/ LRCK BCLK Left Channel DIN/ DOUT 0 n n−1 n−2 Right Channel 2 MSB 1 0 n n−1 n−2 2 1 0 LSB Figure 14.
www.ti.com SLAS412− DECEMBER 2003 D I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of ADWS or LRCK. Similarly the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of ADWS or LRCK. 1/fs ADWS/ LRCK BCLK 1 clock before MSB Left Channel DIN/ DOUT n n−1 n−2 2 1 MSB Right Channel 0 n n−1 n−2 2 1 0 n LSB Figure 16.
www.ti.com SLAS412− DECEMBER 2003 AUDIO DATA CONVERTERS The ’AIC26 has a stereo audio DAC and a mono audio ADC. Both ADC and DAC can operate with a maximum sampling rate of 53 kHz and support all audio standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz. By utilizing the flexible clock generation capability and internal programmable interpolation, a wide variety of sampling rates up to 53 kHz can be obtained from many possible MCLK inputs.
www.ti.com SLAS412− DECEMBER 2003 D When PLL is enabled and D = 0, the following condition must be satisfied 2 MHz v MCLK v 20 MHz P 80 MHz v MCLK P K v 110 MHz 4 v J v 55 D When PLL is enabled and D ≠ 0, the following condition must be satisfied 10 MHz v MCLK v 20 MHz P 80 MHz v MCLK P K v 110 MHz 4 v J v 11 Example 1: For MCLK = 12 MHz and Fsref = 44.1 kHz P = 1, K = 7.5264 ⇒ J = 7, D = 5264 Example 2: For MCLK = 12 MHz and Fsref = 48.0 kHz P = 1, K = 8.
www.ti.com SLAS412− DECEMBER 2003 Automatic Gain Control (AGC) Automatic gain control (AGC) can be used to maintain nominally constant output signal amplitude when recording speech signals. This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone.
www.ti.com SLAS412− DECEMBER 2003 See Table 2 for various AGC programming options. Input Signal Output Signal Target Gain AGC Gain Decay Time Attack Time Figure 18. AGC Characteristics Table 2.
www.ti.com SLAS412− DECEMBER 2003 The DAC digital effects processing block also includes a fourth order digital IIR filter with programmable coefficients (one set per channel).
www.ti.com SLAS412− DECEMBER 2003 The ’AIC26 also includes functionality to detect when the user switches are on or off the de-emphasis or digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the digital effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC.
www.ti.com SLAS412− DECEMBER 2003 0 −2 −4 Gain − dB −6 −8 −10 −12 −14 −16 −18 −20 0 100 200 300 400 500 600 700 800 900 1 k f − Frequency − Hz Figure 19. Uncompensated Response For 16- Load and 50- F Decoupling Capacitor 0 Gain − dB −5 −10 −15 −20 0 100 200 300 400 500 600 700 800 900 1 k f − Frequency − Hz Figure 20.
www.ti.com SLAS412− DECEMBER 2003 ’AIC26 ’AIC26 HPR HPR HPL HPL Headphone Jack VGND VGND Headphone Jack Figure 21. Headphone Configurations, AC-Coupled (left) and Capless (right) The audio output drivers in high power mode can also be configured to drive a mono differential signal into a speaker load of 8-Ω minimum. The speaker load should be connected differentially between the HPR and HPL outputs. Several options are possible for playback of DAC data in this case.
www.ti.com SLAS412− DECEMBER 2003 0 THD − Total Harmonic Distortion − dB −10 −20 2.402 VPP −30 −40 −50 2 VPP −60 −70 −80 −90 −100 0 50 100 150 200 250 300 350 PO − Output Power − mW Figure 23. THD vs Output Power Delivered to an an 8- Load (255C, AVDD = DRVDD = 3.3 V, DVDD = 1.8 V, DAC Output Swing Set to 2 V and 2.4V, and Short-Circuit Protection Disabled) 0 THD − Total Harmonic Distortion − dB −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
www.ti.com SLAS412− DECEMBER 2003 In a third programmable configuration, the ’AIC26 can be programmed to monitor and automatically power down the audio output drivers upon detection of a short-circuit condition (Page2, REG−1DH, bit D7), in addition to setting the short-circuit flag in Page2, REG−1DH, bit−D6. When the device has detected a short and resulted in this condition, the short-circuit flag is cleared when all the routings to the speaker driver are disabled (i.e.
www.ti.com SLAS412− DECEMBER 2003 SPI DIGITAL INTERFACE All ’AIC26 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize transmissions. A transmission begins when initiated by a master SPI.
www.ti.com SLAS412− DECEMBER 2003 Temperature Measurement In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the ’AIC26 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature.
www.ti.com SLAS412− DECEMBER 2003 2700 2500 ADC Code 2300 2100 1900 1700 1500 −40 −20 0 20 40 Temperature − °C 60 80 Figure 26. Typical Plot for Single Measurement Method 500 Differential Code 450 400 350 300 −40 −20 0 20 40 60 80 Temperature − °C Figure 27.
www.ti.com SLAS412− DECEMBER 2003 DC/DC Converter + Battery − VDD VBAT 10 kΩ 2 kΩ GND Figure 28. Battery Measurement Functional Block Diagram For increased protection and robustness, TI recommends a minimum 100-Ω resistor be added in series between the system battery and the VBAT pin. The 100-Ω resistor causes an approximately 1% gain change in the battery voltage measurement, which can easily be corrected in software when the battery conversion data is read by the operating system.
www.ti.com SLAS412− DECEMBER 2003 ’AIC26 COMMUNICATION PROTOCOL Register Programming The ’AIC26 is entirely controlled by registers. An SPI master controlls the reading and writing of these registers by the use of a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown in Figure 29. The command word begins with a R/W bit, which specifies the direction of data flow on the SPI serial bus.
www.ti.com SLAS412− DECEMBER 2003 SS SCLK MOSI COMMAND WORD DATA DATA Figure 30. Write Operation for ’AIC26 SPI Interface SS SCLK MOSI MISO COMMAND WORD DATA Figure 31.
www.ti.com SLAS412− DECEMBER 2003 ’AIC26 MEMORY MAP The ’AIC26 has several 16-bit registers which allow control of the device as well as providing a location for results from the ’AIC26 to be stored until read by the host microprocessor. These registers are separated into three pages of memory in the ’AIC26: a data page (Page 0) and control pages (Page 1 and Page 2). The memory map is shown in Table 6. Table 6.
www.ti.com SLAS412− DECEMBER 2003 ’AIC26 CONTROL REGISTERS This section describes each of the registers shown in the memory map of Table 6. The registers are grouped according to the function they control. In the ’AIC26, bits in control registers can refer to slightly different functions depending on whether you are reading the register or writing to it. ’AIC26 Data Registers (Page 0) The data registers in Page 0 of the ’AIC26 hold data results from auxiliary ADC.
www.ti.com SLAS412− DECEMBER 2003 BIT NAME READ/ WRITE RESET VALUE FUNCTION D7−D6 ADAVG R/W 00 Converter Averaging Control. These two bits allow you to specify the number of averages the converter performs selected by bit D0, which selects either mean filter or median filter. Mean Filter Median filter 00 => No average No average 01 => 4−data average 5-data average 10 => 8−data average 9-data average 11 => 16−data average 15-data average D5−D4 ADCR R/W 00 Conversion Rate Control.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 01H: Status Register BIT NAME READ/ WRITE RESET VALUE D15−D14 DAV R/W 10 Data Available. These two bits program the function of the DAV pin. 00 => Reserved 01 => Acts as data available (Active Low) only. The DAV goes low as soon as one set of ADC conversion is completed. For scan mode, DAV remains low as long as all the appropriate registers have not been read out.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 02H: Reserved BIT NAME D15−D0 READ/ WRITE RESET VALUE R FFFFH FUNCTION Reserved REGISTER 03H: Reference Control NAME READ/ WRITE RESET VALUE R 000H D4 VREFM R/W 0 Voltage Reference Mode. This bit configures the VREF pin as either external reference or internal reference. 0 => External reference 1 => Internal reference D3−D2 RPWUDL R/W 00 Reference Power Up Delay.
www.ti.com SLAS412− DECEMBER 2003 PAGE 2 CONTROL REGISTER MAP REGISTER 00H: Audio Control 1 BIT NAME READ/ WRITE RESET VALUE D15−D14 ADCHPF R/W 00 ADC High Pass Filter 00 => Disabled 01 => −3dB point = 0.0045 x Fs 10 => −3dB point = 0.0125 x Fs 11 => −3dB point = 0.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 01H: CODEC ADC Gain Control BIT NAME READ/ WRITE RESET VALUE D15 ADMUT R/W 1 FUNCTION ADC Channel Mute 1 => ADC channel muted 0 => ADC channel not muted Note: If AGC is enabled, then D15−D8 reflects gain being applied by AGC. If AGC is on, the decoding for read values is as follows: 01110111 => +59.5 dB 01110110 => +59.0 dB −−−−− 00000000 => 0 dB −−−−− 11101001 => −11.
www.ti.com SLAS412− DECEMBER 2003 BIT NAME READ/ WRITE RESET VALUE D4−D1 AGCTC R/W 0000 FUNCTION AGC Time Constant. These four bits set the AGC attack and decay time constants. Time constants remain the same irrespective of any sampling frequency.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 03H: CODEC Sidetone Control BIT NAME READ/ WRITE RESET VALUE D15 ASTMU R/W 1 D14−D8 ASTG R/W 1000101 FUNCTION Analog Sidetone Mute Control 1 => Analog sidetone muted 0 => Analog sidetone not muted Analog Sidetone Gain Setting 0000000 => Analog sidetone gain setting = −34.5 dB 0000001 => Analog sidetone gain setting = −34 dB 0000010 => Analog sidetone gain setting = −33.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 04H: Audio Control 2 BIT NAME READ/ WRITE RESET VALUE D15 KCLEN R/W 0 D14−D12 KCLAC R/W 100 FUNCTION Keyclick Enable 0 => Keyclick disabled 1 => Keyclick enabled Note: This bit is automatically cleared after giving out the keyclick signal length equal to the programmed value. Keyclick Amplitude Control 000 => Lowest amplitude 100 => Medium amplitude 111 => Highest amplitude D11 APGASS R/W 0 ADC Channel PGA Soft-Stepping Control 0 => 0.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 05H: CODEC Power Control BIT NAME READ/ WRITE RESET VALUE D15 PWDNC R/W 1 Codec Power-Down Control 0 => Codec powered up 1 => Codec powered down R 0 Reserved (During read the value of this bit is 0. Write only 0 into this location.
www.ti.com SLAS412− DECEMBER 2003 REGISTER 06H: Audio Control 3 BIT NAME READ/ WRITE RESET VALUE D15−D14 DMSVOL R/W 00 DAC Channel Master Volume Control 00 => Left channel and right channel have independent volume controls 01 => Left channel volume control is the programmed value of the right channel volume control. 10 => Right channel volume control is the programmed value of the left channel volume control. 11 => same as 00 D13 REFFS R/W 0 Reference Sampling Rate.
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www.ti.com SLAS412− DECEMBER 2003 REGISTER 1BH: PLL Programmability BIT NAME READ/ WRITE RESET VALUE D15 PLLSEL R/W 0 D14−D11 QVAL R/W 0010 FUNCTION PLL Enable 0 => Disable PLL 1 => Enable PLL Q value. Valid only if PLL is disabled. 0000 => 16 0001 => 17 0010 => 2 0011 => 3 −−−−− 1100 => 12 1101 => 13 1110 => 14 1111 => 15 D10−D8 PVAL R/W 000 P value.
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www.ti.com SLAS412− DECEMBER 2003 REGISTER 1EH: Audio Control 5 BIT NAME READ/ WRITE RESET VALUE D15−D9 MAX_AGC_PGA R/W 1111111 D8−D6 AGC_NOI_DEB R/W 000 AGC Debounce Time for Speech Mode to Silence Mode Transition 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms −−−−− 110 => 16.0 ms 111 => 32.0 ms D5−D3 AGC_SIG_DEB R/W 000 AGC Debounce Time for Silence Mode to Speech Mode Transition 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms −−−−− 110 => 16.0 ms 111 => 32.
www.ti.com SLAS412− DECEMBER 2003 The ’AIC26 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
www.ti.com SLAS412− DECEMBER 2003 REG−00 of PAGE−01 is updated for Continous AUX SCAN Mode Waiting for Host to write into REG−00 of PAGE−01 SS Deactivated Wait for Reference Powerup Delay in case of internal ref.
www.ti.com SLAS412− DECEMBER 2003 AUDIO CODEC FILTER FREQUENCY RESPONSES Pass-Band Frequency Response of ADC Digital Filter Frequency Response of Full ADC Channel Digital Filter at Fs = 48 kHz 0.02 0 Magnitude − dB −0.02 −0.04 −0.06 −0.06 −0.1 −0.12 −0.14 −0.16 −0.18 0.2 0.4 0.6 0.8 1 1.2 Frequency − Hz 1.4 1.6 1.8 x 104 Frequency Response of ADC High-Pass Filter (Fcut-off = 0.0045 Fs) Frequency Response of ADC HPF at Fs = 48 kHz With −3 dB at 0.
www.ti.com SLAS412− DECEMBER 2003 Frequency Response of ADC High-Pass Filter (Fcut-off = 0.0125 Fs) Frequency Response of ADC HPF at Fs = −48 kHz With −3 dB at 0.0125 Fs 0 −2 −4 Magnitude − dB −6 −8 −10 −12 −14 −16 −18 0 1000 2000 3000 4000 Frequency − Hz 5000 6000 Frequency Response of ADC High-Pass Filter (Fcut-off = 0.025 Fs) Frequency Response of ADC HPF at Fs = 48 kHz With −3 dB at 0.
www.ti.com SLAS412− DECEMBER 2003 DAC CHANNEL DIGITAL FILTER DAC Channel Digital Filter Frequency Response Frequency Response of Full DAC Channel Digital Filterat Fs = 48 kHz 0 −20 Magnitude − dB −40 −60 −80 −100 −120 −140 −160 0 0.5 1 1.5 2 Frequency − Hz 2.5 3 3.5 x 105 DAC Channel Digital Filter Pass-Band Frequency Response Frequency Response of Full DAC Channel Digital Filter at Fs = 48 kHz 0.04 0.02 Magnitude − dB 0 −0.02 −0.04 −0.06 −0.08 −0.1 −0.12 −0.14 0.5 56 1 1.
www.ti.com SLAS412− DECEMBER 2003 DEFAULT DIGITAL AUDIO EFFECTS FILTER RESPONSE AT 48 ksps Frequency Response of 4th Order Effects Filter With Default Coefficients Set 0 Magnitude − dB −0.5 −1 −1.5 −2 −2.
www.ti.com SLAS412− DECEMBER 2003 De-Emphasis Error at 32 ksps De-Emphasis Error With Respect to Ideal Frequency Response For Fs = 33 kHz 0.3 0.25 0.2 Gain − dB 0.15 0.1 0.05 0 −0.05 −0.1 0 2000 4000 6000 8000 10000 12000 Frequency − Hz 14000 16000 De-Emphasis Filter Frequency Response at 44.1 ksps Digital De-Emphasis Frequency Response For Fs = 44.1 kHz 0 −1 −2 Gain − dB −3 −4 −5 −6 −7 −8 −9 −10 0 58 0.5 1 1.
www.ti.com SLAS412− DECEMBER 2003 De-Emphasis Error at 44.1 ksps De-Emphasis Error With Respect to Ideal Frequency Response For Fs = 44.1 kHz 0.3 0.25 0.2 Gain − dB 0.15 0.1 0.05 0 −0.05 −0.1 0 0.5 1 1.5 Frequency − Hz 2 2.5 x 104 De-Emphasis Frequency Response at 48 ksps Digital De-Emphasis Frequency Response at Fs = 48 kHz 0 −1 −2 Gain − dB −3 −4 −5 −6 −7 −8 −9 −10 0 0.5 1 1.5 Frequency − Hz 2 2.
www.ti.com SLAS412− DECEMBER 2003 De-Emphasis Error at 48 ksps De-Emphasis Error With Respect to Ideal Frequency Response For Fs = 48 kHz 0.3 0.25 0.2 Gain − dB 0.15 0.1 0.05 0 −0.05 −0.1 0 0.5 1 1.5 Frequency − Hz 2 2.5 x 104 PLL PROGRAMMING The on-chip PLL in the ’AIC26 can be used to generate sampling clocks from a wide range of MCLK’s available in a system. The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or 48 kHz).
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC26IRHBR Package Package Pins Type Drawing VQFN RHB 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC26IRHBR VQFN RHB 32 3000 338.1 338.1 20.
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