TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY Check for Samples: TLV320AIC3104 FEATURES 1 • • • • • • • • • • • • • • Stereo Audio DAC – 102-dBA Signal-to-Noise Ratio – 16/20/24/32-Bit Data – Supports Sample Rates From 8 kHz to 96 kHz – 3D/Bass/Treble/EQ/De-Emphasis Effects – Flexible Power Saving Modes and Performance are Available Stereo Audio ADC – 92-dBA Signal-to-Noise Ratio – Supports Sample Rates From 8 kHz to 96 kHz
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
Voltage Supplies SW-D3 DINR Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Links: TLV320AIC3104 Audio Clock Generation SW-D1 DINL MCLK Bias/ Reference ADC ADC DOUTR LINE2R LINE1RM + PGA 0/+59.5dB 0.5dB Steps AGC PGA 0/+59.5dB 0.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 1.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 2. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME QFN NO. I/O AVDD 25 — Analog DAC voltage supply, 2.7 V–3.6 V AVSS1 17 — Analog ADC ground supply, 0 V AVSS2 26 — Analog DAC ground supply, 0 V BCLK 2 I/O Audio serial data bus bit clock input/output DIN 4 I Audio serial data bus data input DOUT 5 O Audio serial data bus data output DRVDD 18 — Analog ADC and output driver voltage supply, 2.7 V–3.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT AVDD to AVSS, DRVDD to DRVSS –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD TJ Max –0.1 to 0.1 V Digital input voltage to DVSS –0.3 to IOVDD + 0.3 V Analog input voltage to AVSS –0.3 to AVDD + 0.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC Input signal level SNR Signal-to-noise ratio Dynamic range THD Single-ended (1) (2) (1) (2) Total harmonic distortion PSRR Power-supply rejection ratio 0.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS Full-scale output voltage Signal-to-noise ratio PSRR (3) MIN 0-dB input full-scale signal, output common-mode setting = 1.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC DIGITAL INTERPOLATION – FILTER fS = 48 kHz Pass band 0 Pass-band ripple Hz dB Transition band 0.45 fS 0.55 fS Hz Stop band 0.55 fS 7.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IIN IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD IDRVDD + IAVDD IDVDD (6) 10 TEST CONDITIONS MIN TYP 0.1 RESET held low 0.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS THD − Total Harmonic Distortion − dB 0 Load = 16 Ω AC-Coupled −10 HPL DRVDD = 2.7 V −20 −30 HPR DRVDD = 2.7 V −40 HPL DRVDD = 3.3 V HPR DRVDD = 3.3 V −50 HPR DRVDD = 3.6 V −60 HPL DRVDD = 3.6 V −70 −80 0 10 20 30 40 50 60 70 80 90 100 P − Headphone Power − mW G001 Figure 5.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD DSP or Apps Processor 0.1 mF AVDD_DAC DRVDD DRVDD MIC1LP/LINE1LP MIC1LM/LINE1LM 1 kW A AVDD (2.7 V–3.6 V) 0.1 mF 0.1 mF 0.1 mF 1 mF 0.1 mF 0.47 mF FM Tuner MIC2L/LINE2L MIC2R/LINE2R IOVDD TLV320AIC3104 0.47 mF MIC1RP/LINE1RP 1.525 V–1.95 V LEFT_LOP LEFT_LOM RIGHT_ROM HPROUT HPLOUT HPRCOM HPLCOM 1 mF 1 mF 0.1 mF MIC1RM/LINE1RM 0.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) IOVDD DSP or Apps Processor AVDD_DAC DRVDD DRVDD MIC1LP/LINE1LP MIC1LM/LINE1LM 1 kW A AVDD (2.7 V–3.6 V) 0.1 mF 1 mF 1 mF 0.1 mF 0.47 mF FM Tuner MIC2L/LINE2L MIC2R/LINE2R IOVDD TLV320AIC3104 0.47 mF MIC1RP/LINE1RP 1.525 V–1.95 V 0.1 mF 1 mF 1 mF 0.1 mF LEFT_LOP LEFT_LOM RIGHT_ROM RIGHT_ROP HPROUT HPLOUT HPRCOM HPLCOM A IOVDD (1.1 V–3.3 V) DVSS MIC1RM/LINE1RM 0.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com OVERVIEW The TLV320AIC3104 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications. Available in a 5-mm × 5-mm, 32-lead QFN, the product integrates a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 DIGITAL CONTROL SERIAL INTERFACE The register map of the TLV320AIC3104 actually consists of two pages of registers, with each page containing 128 registers. The register at address zero on each page is used as a page-control register, and writing to this register determines the active page for the device.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 I2C BUS DEBUG IN A GLITCHED SYSTEM Occasionally, some systems may encounter noise or glitches on the I2C bus. In the unlikely event that this affects bus performance, then it can be useful to use the I2C Debug register. This feature terminates the I2C bus error allowing this I2C device and system to resume communications. The I2C bus error detector is enabled by default.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com RIGHT-JUSTIFIED MODE In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock. 1/fs WCLK BCLK Right Channel Left Channel SDIN/SDOUT 0 2 n–1 n–2 n–3 MSB 1 n–1 n–2 n–3 0 2 1 0 LSB T0149-01 Figure 18.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. 1/fs WCLK BCLK 1 Clock Before MSB Right Channel Left Channel SDIN/SDOUT 2 n–1 n–2 n–3 0 1 MSB 2 n–1 n–2 n–3 0 1 n–1 LSB T0151-01 2 Figure 20.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com TDM DATA TRANSFER Time-division multiplexed data transfer can be realized in any of the left- transfer modes if the 256-clock bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 The sampling rate of the ADC and DAC can be set to fS(ref)/NCODEC or 2 × fS(ref)/NCODEC, with NCODEC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3104, NDAC and NADC must be set to the same value, as the device only supports a common sample rate for the ADC and DAC channels.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 The following table lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1 kHz or 48 kHz. fS(ref) = 44.1 kHz MCLK (MHz) P R J 2.8224 1 1 32 D 0 ACHIEVED fS(ref) 44,100 % ERROR 0 5.6448 1 1 16 0 44,100 0 12 1 1 7 5264 44,100 13 1 1 6 9474 44,099.71 16 1 1 5 6448 44,100 19.2 1 1 4 7040 44,100 19.68 1 1 4 5893 44,100.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed.
TLV320AIC3104 BCLK WCLK SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 DIN DOUT www.ti.com AGC DINR DINL DOUTL DOUTR Digital Audio Data Serial Interface DAC Powered Down Record Path SW-D2 Left-Channel Analog Inputs + PGA 0 dB–59.5 dB, 0.5-dB Steps Effects ADC Volume Control DAC L SW-D1 DAC Powered Down Record Path AGC SW-D4 Right-Channel Analog Inputs + PGA 0 dB–59.5 dB, 0.5-dB Steps Effects ADC SW-D3 Volume Control DAC R B0173-01 Figure 24.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed by writing to page 0, register 103, and the left channel is programmed by writing to page 0, register 105. Decay time determines how quickly the PGA gain is increased when the input signal is too low.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Input Signal Output Signal Target Level AGC Gain Decay Time Attack Time W0002-01 Figure 25. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the fS(ref) value programmed in the control registers.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see page 1, registers 21–26 for the left channel and page 1, registers 47–52 for the right channel).
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 6.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com DELTA-SIGMA AUDIO DAC The stereo audio DAC incorporates a third-order multi-bit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a continuous-time RC filter. The analog FIR operates at a rate of 128 fS(ref) (6.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 7. Appropriate Settings CM SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD 1.35 2.7 V–3.6 V 1.525 V–1.95 V 1.5 3 V–3.6 V 1.65 V–1.95 V 1.65 V 3.3 V–3.6 V 1.8 V–1.95 V 1.8 V 3.6 V 1.95 V AUDIO DAC POWER CONTROL The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can be powered up or down independently.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com ANALOG INPUT BYPASS PATH FUNCTIONALITY The TLV320AIC3104 includes the additional ability to route some analog input signals past the integrated data converters, for mixing with other analog signals and then direct connection to the output drivers. This capability is useful in a cellphone, for example, when a separate FM radio device provides a stereo analog output signal that needs to be routed to headphones.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Connecting the MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SWL0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the MIC2L/LINE2L input signal to the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0; this action is done by writing a 1 to page 0, register 108, bit D2.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC3104 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 30 and Figure 31.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 PGA_L 0 dB to –78 dB PGA_R 0 dB to –78 dB + DAC_L1 0 dB to –78 dB DAC_R1 0 dB to –78 dB B0158-01 Figure 31. Detail of the Volume Control and Mixing Function Shown in Figure 26 and Figure 16 The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the requirements of the system.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com The output stage architecture leading to the high-power output drivers is shown in Figure 32, with the volume control and mixing blocks being effectively identical to those shown in Figure 31. Note that each of these drivers has an output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output signal.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. The user should first program the type of output configuration being used in page 0, register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com MICBIAS g Stereo s AVDD s MIC2L/LINE2L/MICDET To Detection Block MIC2R Cellular g MIC PreAmp s m HPLOUT Stereo + Cellular g m s Pwr Amp s HPROUT m = mic s = ear speaker g = ground/vcm Pwr Amp HPRCOM HPLCOM Pwr Amp To Detection Block 1.35 V B0243-02 Figure 33.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 35. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to ground if the plug is removed, which can be implemented using a spring terminal in a jack.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Page 0/Register 2: Codec Sample Rate Select Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3–D0 R/W 0000 (1) DESCRIPTION ADC Sample Rate Select (1) 0000: ADC fS = fS(ref)/1 0001: ADC fS = fS(ref)/1.5 0010: ADC fS = fS(ref)/2 0011: ADC fS = fS(ref)/2.5 0100: ADC fS = fS(ref)/3 0101: ADC fS = fS(ref)/3.5 0110: ADC fS = fS(ref)/4 0111: ADC fS = fS(ref)/4.5 1000: ADC fS = fS(ref)/5 1001: ADC fS = fS(ref)/5.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Page 0/Register 4: PLL Programming Register B BIT D7–D2 READ/ WRITE R/W RESET VALUE 0000 01 D1–D0 R/W 00 DESCRIPTION PLL J Value 0000 00: Reserved, do not write this sequence 0000 01: J = 1 0000 10: J = 2 0000 11: J = 3 … 1111 10: J = 62 1111 11: J = 63 Reserved. Write only zeros to these bits. Page 0/Register 5: PLL Programming Register C (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION PLL D Value.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Page 0/Register 8: Audio Serial Data Interface Control Register A BIT D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 D2 R/W R/W 0 0 D1–D0 R/W 00 DESCRIPTION Bit Clock Directional Control 0: BCLK is an input (slave mode). 1: BCLK is an output (master mode). Word Clock Directional Control 0: WCLK is an input (slave mode). 1: WCLK is an output (master mode).
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Page 0/Register 10: Audio Serial Data Interface Control Register C BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 READ/ WRITE R RESET VALUE 0 DESCRIPTION Audio Serial Data Word Offset Control This register determines where valid data is placed or expected in each frame, by controlling the offset from beginning of the frame where valid data begins. The offset is measured from the rising edge of word clock when in DSP mode.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Page 0/Register 12: Audio Codec Digital Filter Control Register BIT D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D4 R/W 00 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R 00 D4–D2 R/W 000 D1–D0 R/W 00 DESCRIPTION Left-ADC High-Pass Filter Control 00: Left-ADC high-pass filter disabled 01: Left-ADC high-pass filter –3-dB frequency = 0.
TLV320AIC3104 www.ti.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Page 0/Register 17: MIC2L/R to Left-ADC Control Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 1111 D3–D0 R/W 1111 DESCRIPTION MIC2L Input Level Control for Left-ADC PGA Mix Setting the input level control to one of the following gains automatically connects MIC2L to the left-ADC PGA mix. 0000: Input level control gain = 0 dB 0001: Input level control gain = –1.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Page 0/Register 19: MIC1LP/LINE1LP to Left-ADC Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 1111 D2 R/W 0 D1–D0 R/W 00 DESCRIPTION MIC1LP/LINE1LP Single-Ended vs Fully Differential Control. If MIC1LP/LINE1LP is selected to both leftand right-ADC channels, both connections must use the same configuration (single-ended or fully differential mode). 0: MIC1LP/LINE1LP is configured in single-ended mode.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Page 0/Register 22: MIC1RP/LINE1RP to Right-ADC Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 1111 D2 R/W 0 D1–D0 R/W 00 DESCRIPTION MIC1RP/LINE1RP Single-Ended vs Fully Differential Control. If MIC1RP/LINE1RP is selected to both leftand right-ADC channels, both connections must use the same configuration (single-ended or fully differential mode). 0: MIC1RP/LINE1RP is configured in single-ended mode.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Page 0/Register 25: MICBIAS Control Register BIT D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D3 D2–D0 R R 000 XXX BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 DESCRIPTION MICBIAS Level Control 00: MICBIAS output is powered down. 01: MICBIAS output is powered to 2 V. 10: MICBIAS output is powered to 2.5 V. 11: MICBIAS output is connected to AVDD. Reserved. Write only zeros to these bits.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Page 0/Register 28: Left-AGC Control Register C BIT D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D1 R/W 00 000 D0 R/W 0 DESCRIPTION Noise Gate Hysteresis Level Control 00: Hysteresis = 1 dB 01: Hysteresis = 2 dB 10: Hysteresis = 3 dB 11: Hysteresis is disabled.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Page 0/Register 31: Right-AGC Control Register C BIT D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D1 R/W 00 000 D0 R/W 0 DESCRIPTION Noise Gate Hysteresis Level Control 00: Hysteresis = 1 dB 01: Hysteresis = 2 dB 10: Hysteresis = 3 dB 11: Hysteresis is disabled.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 8. Page 0/Register 34: Left-AGC Noise Gate Debounce Register BIT D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 (1) DESCRIPTION Left-AGC Noise Detection Debounce Control These times (1) are not accurate when double-rate audio mode is enabled. 0000 0: Debounce = 0 ms 0000 1: Debounce = 0.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 10. Page 0/Register 36: ADC Flag Register BIT D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 R 0 D4 R 0 D3 R 0 D2 R 0 D1 R 0 D0 R 0 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3–D0 R 000 DESCRIPTION Left-ADC PGA Status 0: Applied gain and programmed gain are not the same. 1: Applied gain = programmed gain Left-ADC Power Status 0: Left ADC is in a power-down state.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 12. Page 0/Register 38: High-Power Output Driver Control Register BIT D7–D6 D5–D3 READ/ WRITE R R/W RESET VALUE 00 000 D2 R/W 0 D1 R/W 0 D0 R 0 DESCRIPTION Reserved. Write only zeros to these register bits.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 16.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Output Stage Volume Controls A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 19. Output Stage Volume Control Settings and Gains Gain Setting Analog Gain (dB) Gain Setting 0 0 30 1 –0.5 2 –1 3 Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) –15 60 –30.1 90 –45.2 31 –15.5 61 –30.6 91 –45.8 32 –16 62 –31.1 92 –46.2 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2 34 –17 64 –32.1 94 –47.4 5 –2.5 35 –17.5 65 –32.6 95 –47.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 22. Page 0/Register 47: DAC_L1 to HPLOUT Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION DAC_L1 Output Routing Control 0: DAC_L1 is not routed to HPLOUT. 1: DAC_L1 is routed to HPLOUT. DAC_L1 to HPLOUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 19. Table 23.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 28. Page 0/Register 53: PGA_L to HPLCOM Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 DESCRIPTION PGA_L Output Routing Control 0: PGA_L is not routed to HPLCOM. 1: PGA_L is routed to HPLCOM. PGA_L to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 19. Table 29.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 33. Page 0/Register 58: HPLCOM Output Level Control Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 BIT READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION HPLCOM Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 39. Page 0/Register 64: DAC_R1 to HPROUT Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 DESCRIPTION DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPROUT. 1: DAC_R1 is routed to HPROUT.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 45. Page 0/Register 70: PGA_R to HPRCOM Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 DESCRIPTION PGA_R Output Routing Control 0: PGA_R is not routed to HPRCOM. 1: PGA_R is routed to HPRCOM. PGA_R to HPRCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 19. Table 46.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 51. Page 0/Register 81: PGA_L to LEFT_LOP/M Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 DESCRIPTION PGA_L Output Routing Control 0: PGA_L is not routed to LEFT_LOP/M. 1: PGA_L is routed to LEFT_LOP/M. PGA_L to LEFT_LOP/M Analog Volume Control For 7-bit register settings versus analog gain values, see Table 19. Table 52.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 56. Page 0/Register 86: LEFT_LOP/M Output Level Control Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 DESCRIPTION LEFT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 62. Page 0/Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 BIT D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 D4 R R 0 0 D3 R 0 D2 R 0 D1 R 0 D0 R 0 DESCRIPTION DAC_R1 Output Routing Control 0: DAC_R1 is not routed to RIGHT_LOP/M.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 65.
TLV320AIC3104 www.ti.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 69. Page 0/Register 103: Left-AGC New Programmable Attack Time Register BIT D7 READ/ WRITE R/W RESET VALUE 0 DESCRIPTION D6–D5 R/W 00 D4–D2 R/W 000 Attack Time Register Selection 0: Attack time for the left AGC is generated from page 0, register 26. 1: Attack time for the left AGC is generated from this register.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 71. Page 0/Register 105: Right-AGC New Programmable Attack Time Register BIT D7 READ/ WRITE R/W RESET VALUE 0 DESCRIPTION D6–D5 R/W 00 D4–D2 R/W 000 Attack Time Register Selection 0: Attack time for the right AGC is generated from page 0, register 29. 1: Attack time for the right AGC is generated from this register.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.com Table 73. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3 R/W 0 D2 R/W 0 D1 D0 R R 0 0 DESCRIPTION Left-Channel High-Pass Filter Coefficient Selection 0: Default coefficients are used when ADC high pass is enabled. 1: Programmable coefficients are used when ADC high pass is enabled.
TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Table 76. Page 0/Register 110–127: Reserved Registers BIT READ/ WRITE R RESET VALUE 0000 0000 READ/ WRITE RESET VALUE D7–D1 X 0000 000 D0 R/W 0 D7–D0 DESCRIPTION Reserved. Do not write to these registers. Page 1/Register 0: Page Select Register BIT DESCRIPTION Reserved, write only zeros to these bits. Page Select Bit Writing zero to this bit sets page 0 as the active page for following register accesses.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.
TLV320AIC3104 www.ti.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.
TLV320AIC3104 www.ti.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.
TLV320AIC3104 www.ti.
TLV320AIC3104 SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 www.ti.
TLV320AIC3104 www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3104IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3104IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3104IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3104IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3104IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TLV320AIC3104IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC3104IRHBT VQFN RHB 32 250 210.0 185.0 35.
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