Datasheet

N–1
N–1
N–1
1
1
1
1N–1N–2
N–2
N–2
0
0
0
0
N–2
Right-ChannelData
Right-ChannelData
Left-ChannelData
Left-ChannelData
••••
••••
••••
•••• ••
DSP Mode
Left-JustifiedMode
Offset
Offset Offset
T0153-01
WordClock
WordClock
BitClock
BitClock
DataIn/Out
DataIn/Out
AUDIO DATA CONVERTERS
AUDIO CLOCK GENERATION
TLV320AIC3105
www.ti.com ......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
Figure 21. DSP Mode and Left-Justified Modes, Showing the
Effect of a Programmed Data Word Offset
The TLV320AIC3105 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, which are described further below.
The data converters are based on the concept of an f
S(ref)
rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f
S(ref)
is either
44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional
restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and
also to enable high quality playback of low sampling rate data, without high frequency audible noise being
generated.
The sampling rate of the ADC and DAC can be set to f
S(ref)
/NDAC or 2 × f
S(ref)
/NDAC, with NDAC being 1, 1.5, 2,
2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3105, the NDAC and
NADC should be set to the same value, as the device only supports a common sample rate for the ADC and
DAC channels. Therefore, NCODEC = NDAC = NDAC, and this is programmed by setting the value of bits
D7 – D4 equal to the value of bits D3 – D0 in page 0, register 2.
The audio converters in the TLV320AIC3105 need an internal audio master clock at a frequency of 256 × f
S(ref)
,
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC3105 is shown in Figure 22 .
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