Datasheet
TLV320AIC3105
www.ti.com
......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as
high as 50 MHz, and f
S(ref)
should fall within 39 kHz to 53 kHz. (In the TLV320AIC3105, the NDAC setting must
be the same as the NADC setting. The NDAC ratio is set on page 0, register 2. The NDAC is set equal to NADC
by setting the value of bits D7 – D4 equal to that of bits D3 – D0.)
When the PLL is enabled,
f
S(ref)
= (PLLCLK_IN × K × R)/(2048 × P), where
P = 1, 2, 3, … , 8
R = 1, 2, … , 16
K = J.D
J = 1, 2, 3, … , 63
D = 0000, 0001, 0002, 0003, … , 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by page 0, register 102, bits D5 – D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ ( PLLCLK_IN/P ) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R/P ) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:
10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and f
S(ref)
= 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and f
S(ref)
= 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve f
S(ref)
= 44.1 kHz or 48 kHz.
f
S(ref)
= 44.1 kHz
MCLK (MHz) P R J D ACHIEVED f
S(ref)
% ERROR
2.8224 1 1 32 0 44,100 0
5.6448 1 1 16 0 44,100 0
12 1 1 7 5264 44,100 0
13 1 1 6 9474 44,099.71 – 0.0007
16 1 1 5 6448 44,100 0
19.2 1 1 4 7040 44,100 0
19.68 1 1 4 5893 44,100.3 0.0007
48 4 1 7 5264 44,100 0
f
S(ref)
= 48 kHz
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