Datasheet
Au
dio Serial Bus Interface
I
2
C Serial
Con
trol Bus
Bias/
Re
ference
MICBIAS
SCL
SDA
RESET
Volta
ge Supplies
A
udio Clock
Ge
neration
MCLK
MIC2L/LINE2L
LINE2L
M
IC3L/LINE3L/MICDET
MIC1L/LINE1L
LI
NE1L
PG
A
0/+5
9.5dB
0.5d
B
S
teps
ADC
+
+
+
+
+
+
VCM
VC
M
DAC
L
+
Volume
Co
ntrol
Eff
ects
DIN
DOUT
BCLK
WCLK
DINL
DINR
DOUTL
DOUTR
MIC2R/LINE2R
L
INE2R
MIC3R/LINE3R
ADC
PGA
0/+59.5dB
0.5dB
Steps
+
MIC1R/LINE1R
L
INE1R
DA
C
R
Volume
Con
trol
Effects
A
GC
AGC
SW-D2
SW-D1
SW-D3
SW-D4
DVDD
DRVDD
DRVDD
DRVSS
DVSS
IOVDD
AVSS_ADC
AVDD_DAC
AVSS_DAC
HPROUT
HPRCOM
HPLCOM
HPLOUT
LEF
T_LOP
LEFT
_LOM
LIN
E1L
LINE2L
SW
-L0
SW
-L1
SW-L2
RIGHT_LOP
RIG
HT_LOM
LINE1R
LINE2R
SW-R0
SW-R1
SW-R2
B0152-01
TLV320AIC3105
www.ti.com
......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
SIMPLIFIED BLOCK DIAGRAM
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