Datasheet
TLV320AIC3105
www.ti.com
......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 0/Register 21: LINE1R to Left-ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved
D6 – D3 R/W 1111 LINE1R Input Level Control for Left-ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the left-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = – 1.5 dB
0010: Input level control gain = – 3 dB
0011: Input level control gain = – 4.5 dB
0100: Input level control gain = – 6 dB
0101: Input level control gain = – 7.5 dB
0110: Input level control gain = – 9 dB
0111: Input level control gain = – 10.5 dB
1000: Input level control gain = – 12 dB
1001 – 1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1R is not connected to the left-ADC PGA.
D2 – D0 R 000 Reserved. Write only zeros to these register bits.
Page 0/Register 22: LINE1R to Right ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved
D6 – D3 R/W 1111 LINE1R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the right ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = – 1.5 dB
0010: Input level control gain = – 3 dB
0011: Input level control gain = – 4.5 dB
0100: Input level control gain = – 6 dB
0101: Input level control gain = – 7.5 dB
0110: Input level control gain = – 9 dB
0111: Input level control gain = – 10.5 dB
1000: Input level control gain = – 12 dB
1001 – 1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1R is not connected to the right ADC PGA.
D2 R/W 0 Right ADC Channel Power Control
0: Right ADC channel is powered down.
1: Right ADC channel is powered up.
D1 – D0 R/W 00 Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per f
S
01: Right ADC PGA soft-stepping at once per two f
S
10 – 11: Right ADC PGA soft-stepping is disabled.
Page 0/Register 23: LINE2R to Right ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved
D6 – D3 R/W 1111 LINE2R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2R to the right ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = – 1.5 dB
0010: Input level control gain = – 3 dB
0011: Input level control gain = – 4.5 dB
0100: Input level control gain = – 6 dB
0101: Input level control gain = – 7.5 dB
0110: Input level control gain = – 9 dB
0111: Input level control gain = – 10.5 dB
1000: Input level control gain = – 12 dB
1001 – 1110: Reserved. Do not write these sequences to these register bits.
1111: LINE2R is not connected to the right ADC PGA.
D2 R/W 0 Right ADC Channel Weak Common-Mode Bias Control
0: Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage.
1: Right ADC channel unselected inputs are biased weakly to the ADC common-mode voltage.
D1 – D0 R 00 Reserved. Write only zeros to these register bits
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