Datasheet

TLV320AIC3105
SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com
Page 0/Register 91: PGA_R to RIGHT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to RIGHT_LOP/M
1: PGA_R is routed to RIGHT_LOP/M
D6 – D0 R/W 000 0000 PGA_R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 6
Page 0/Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to RIGHT_LOP/M.
1: DAC_R1 is routed to RIGHT_LOP/M.
D6 – D0 R/W 000 0000 DAC_R1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 6
Page 0/Register 93: RIGHT_LOP/M Output Level Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D4 R/W 0000 RIGHT_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010 – 1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 RIGHT_LOP/M Mute
0: RIGHT_LOP/M is muted
1: RIGHT_LOP/M is not muted
D2 R 0 Reserved. Don ’ t write to this register bit.
D1 R 1 RIGHT_LOP/M Volume Control Status
0: All programmed gains to RIGHT_LOP/M have been applied
1: Not all programmed gains to RIGHT_LOP/M have been applied yet
D0 R 0 RIGHT_LOP/M Power Status
0: RIGHT_LOP/M is not fully powered up.
1: RIGHT_LOP/M is fully powered up.
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