Datasheet
TLV320AIC3105
www.ti.com
......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 1/Register 50: Right Channel De-Emphasis Filter N1 Coefficient LSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0010 1101 Right Channel De-Emphasis Filter N1 Coefficient LSB. The 16-bit integer contained in the MSB and LSB
registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from
– 32,768 to 32,767.
Page 1/Register 51: Right Channel De-Emphasis Filter D1 Coefficient MSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0101 0011 Right Channel De-Emphasis Filter D1 Coefficient MSB. The 16-bit integer contained in the MSB and LSB
registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from
– 32,768 to 32,767.
Page 1/Register 52: Right Channel De-Emphasis Filter D1 Coefficient LSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0111 1110 Right Channel De-Emphasis Filter D1 Coefficient LSB. The 16-bit integer contained in the MSB and LSB
registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from
– 32,768 to 32,767.
Page 1/Register 53: 3-D Attenuation Coefficient MSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0111 1111 3-D Attenuation Coefficient MSB. The 16-bit integer contained in the MSB and LSB registers for this
coefficient are interpreted as a 2s-complement integer, with possible values ranging from – 32,768 to
32,767.
Page 1/Register 54: 3-D Attenuation Coefficient LSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 1111 1111 3-D Attenuation Coefficient LSB. The 16-bit integer contained in the MSB and LSB registers for this
coefficient are interpreted as a 2s-complement integer, with possible values ranging from – 32,768 to
32,767.
Page 1/Register 55 – 64: Reserved Registers
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R 0000 0000 Reserved. Do not write to these registers.
Page 1/Register 65: Left Channel ADC High-Pass Filter N0 Coefficient MSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0011 1001 Left Channel ADC High-Pass Filter N0 Coefficient MSB. The 16-bit integer contained in the MSB and LSB
registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from
– 32,768 to 32,767.
Page 1/Register 66: Left Channel ADC High-Pass Filter N0 Coefficient LSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0101 0101 Left Channel ADC High-Pass Filter N0 Coefficient LSB. The 16-bit integer contained in the MSB and LSB
registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from
– 32,768 to 32,767.
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