Datasheet

TLV320AIC3105
www.ti.com ......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 1/Register 75: Right Channel ADC High-Pass Filter D1 Coefficient MSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0101 0011 Right Channel ADC High-Pass Filter D1 Coefficient MSB. The 16-bit integer contained in the MSB and
LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging
from – 32,768 to 32,767.
Page 1/Register 76: Right Channel ADC High-Pass Filter D1 Coefficient LSB Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0111 1110 Right Channel ADC High-Pass Filter D1 Coefficient LSB. The 16-bit integer contained in the MSB and
LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging
from – 32,768 to 32,767.
Page 1/Register 77 – 127: Reserved Registers
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R 0000 0000 Reserved. Do not write to these registers.
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