TLV320AIC3105 www.ti.com.........................................................................................................................................
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3105 MIC2R/LINE2R MIC3R/LINE3R MIC1R/LINE1R MIC1L/LINE1L MIC3L/LINE3L/MICDET LINE2R LINE1R LINE1L Voltage Supplies + + SW-D1 DOUTL SW-D3 Audio Clock Generation ADC ADC DOUTR MCLK Bias/ Reference PGA 0/+59.5dB 0.5dB Steps AGC PGA 0/+59.5dB 0.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME QFN NO. I/O AVDD 25 I Analog DAC voltage supply, 2.7 V–3.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TJ Max (2) VALUE UNIT AVDD to AVSS, DRVDD to DRVSS –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD –0.1 to 0.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 2.3 2.455 MAX UNIT MICROPHONE BIAS Programmable setting = 2 V Bias voltage 2 Programmable setting = 2.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO DAC – Lineout and Headphone Out Drivers First option Output common mode 1.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS THD − Total Harmonic Distortion − dB 0 Load = 16 Ω AC-Coupled −10 HPL DRVDD = 2.7 V −20 −30 HPR DRVDD = 2.7 V −40 HPL DRVDD = 3.3 V HPR DRVDD = 3.3 V −50 HPR DRVDD = 3.6 V −60 HPL DRVDD = 3.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) 0 −20 Amplitude − dB −40 −60 −80 −100 −120 −140 −160 0 2 4 6 8 10 12 14 16 18 20 f − Frequency − kHz G004 Figure 7.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) 0.85 Left ADC 0.8 0.75 Right ADC Gain Error (dB) 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0 10 20 30 40 PGA Setting (dB) 50 60 70 G009 Figure 9. ADC Gain Error vs PGA Gain Setting 3.6 MICBIAS Output Voltage − V 3.4 3.2 MICBIAS = AVDD 3.0 2.8 2.6 MICBIAS = 2.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) 3.2 MICBIAS Output Voltage − V 3.0 MICBIAS = AVDD 2.8 2.6 MICBIAS = 2.5 V 2.4 2.2 MICBIAS = 2 V 2.0 1.8 −45 −35 −25 −15 −5 5 15 25 35 45 55 65 TA − Ambient Temperature − °C 75 85 G008 Figure 11.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD DSP or Apps Processor RP 2 kW AVDD (2.7 V – 3.6 V) DIN DOUT BCLK WCLK MCLK RESET MICBIAS SDA SCL RP AVDD_DAC 0.1 mF DRVDD MIC1L/LINE1L 0.47 mF 1 mF 1 mF 0.1 mF 1 mF 10 mF A 0.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) IOVDD DSP or Apps Processor RP 2 kW AVDD (2.7 V – 3.6 V) DIN DOUT BCLK WCLK MCLK RESET MICBIAS SDA SCL RP AVDD_DAC 0.1 mF DRVDD MIC1L/LINE1L 0.47 mF 1 mF 1 mF 0.1 mF 1 mF 10 mF A 0.1 mF MIC2L/LINE2L FM Tuner A MIC2R/LINE2R 0.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 OVERVIEW The TLV320AIC3105 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com SDA tHD-STA ³ 0.9 ms SCL tSU-STA ³ 0.9 ms tSU-STO ³ 0.9 ms tHD-STA ³ 0.9 ms S Sr P S T0114-02 2 Figure 14. I C Interface Timing Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 The TLV320AIC3105 also responds to and acknowledges a General Call, which consists of the master issuing a command with a slave address byte of 00H.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 1/fs WCLK BCLK Right Channel Left Channel SDIN/SDOUT 0 n–1 n–2 n–3 1 2 MSB 0 n–1 n–2 n–3 2 1 0 n–1 n–2 LSB T0150-01 Figure 18.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com 1/fs WCLK BCLK Right Channel Left Channel SDIN/SDOUT n–1 n–2 n–3 n–4 LSB MSB 2 1 0 n–1 n–2 n–3 LSB MSB 2 1 0 n–1 LSB T0152-01 Figure 20.
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TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com MCLK BCLK PLL_CLKIN CLKDIV_CLKIN CLKDIV_IN Q = 2, 3,….., 16, 17 PLL_IN K*R/P 2/Q CLKDIV_OUT K = J.D J = 1, 2, 3, ...., 62, 63 D = 0000, 0001, ...., 9998, 9999 R = 1, 2, 3, 4, ...., 15, 16 P = 1, 2, ....
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz. (In the TLV320AIC3105, the NDAC setting must be the same as the NADC setting. The NDAC ratio is set on page 0, register 2.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com MCLK (MHz) P R J D ACHIEVED fS(ref) % ERROR 2.048 1 1 48 0 48,000 0 3.072 1 1 32 0 48,000 0 4.096 1 1 24 0 48,000 0 6.144 1 1 16 0 48,000 0 8.192 1 1 12 0 48,000 0 12 1 1 8 1920 48,000 13 1 1 7 5618 47,999.71 16 1 1 6 1440 48,000 19.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 H(z) + N0 ) N1 z *1 32, 768 * D1 z *1 (1) Programming the left channel is done by writing to page 1, registers 65–70, and the right channel is programmed by writing to page 1, registers 71–76.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com AUTOMATIC GAIN CONTROL (AGC) An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired).
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Table 4.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 DELTA-SIGMA AUDIO DAC The stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Table 5. Appropriate Settings CM SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD 1.35 2.7 V–3.6 V 1.525 V–1.95 V 1.5 3 V–3.6 V 1.65 V–1.95 V 1.65 V 3.3 V–3.6 V 1.8 V–1.95 V 1.8 V 3.6 V 1.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Gain = 0, –1.5, –3, . . ., –12 dB, Mute MIC1L/LINE1L Gain = 0, –1.5, –3, . . ., –12 dB, Mute MIC2L/LINE2L Gain = 0, –1.5, –3, . . ., –12 dB, Mute To Left ADC PGA MIC1R/LINE1R Gain = 0, –1.5, –3, . . ., –12 dB, Mute MIC3L/LINE3L/MICDET Gain = 0, –1.5, –3, . . .
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described above, the TLV320AIC3105 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the output drivers.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 LINE2L LINE2L MIC2L/LINE2L LINE1L SW-L2 SW-L1 SW-L0 LEFT_LOP LINE1L LEFT_LOM MIC1L/LINE1L LINE1R LINE2R SW-R2 MIC1R/LINE1R LINE1R SW-R1 SW-R0 RIGHT_LOP LINE2R RIGHT_LOM MIC2R/LINE2R B0174-02 Figure 28.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC3105 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 29 and Figure 30.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 MIC2L/LINE2L 0 dB to –78 dB MIC2R/LINE2R 0 dB to –78 dB PGA_L 0 dB to –78 dB + PGA_R 0 dB to –78 dB DAC_L1 0 dB to –78 dB DAC_R1 0 dB to –78 dB B0158-02 Figure 30.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com The output stage architecture leading to the high-power output drivers is shown in Figure 31, with the volume control and mixing blocks being effectively identical to that shown in Figure 30.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com MICBIAS g Stereo s AVDD s MIC3L/LINE3L/MICDET To Detection Block MIC3R g Cellular MIC PreAmp s m HPLOUT Stereo + Cellular g m s Pwr Amp s HPROUT m = mic s = ear speaker g = ground/vcm Pwr Amp HPRCOM HPLCOM Pwr Amp To Detection Block 1.35 V B0243-03 Figure 32.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 34.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Page 0/Register 2: Codec Sample Rate Select Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3–D0 R/W 0000 DESCRIPTION ADC Sample Rate Select 0000: ADC fS = fS(ref)/1 0001: ADC fS = fS(ref)/1.5 0010: ADC fS = fS(ref)/2 0011: ADC fS = fS(ref)/2.
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TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Page 0/Register 4: PLL Programming Register B BIT D7–D2 READ/ WRITE R/W RESET VALUE 0000 01 D1–D0 R/W 00 DESCRIPTION PLL J Value 0000 00: Reserved; do not write this sequence. 0000 01: J = 1 0000 10: J = 2 0000 11: J = 3 … 1111 10: J = 62 1111 11: J = 63 Reserved.
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TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 34: Left-AGC Noise Gate Debounce Register BIT D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 (1) DESCRIPTION Left-AGC Noise Detection Debounce Control These times (1) are not accurate when double-rate audio mode is enabled. 0000 0: Debounce = 0 ms 0000 1: Debounce = 0.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.
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TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 44: Right DAC Digital Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0000 DESCRIPTION Right DAC Digital Mute 0: The right DAC channel is not muted. 1: The right DAC channel is muted.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Table 6. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 27 –13.5 57 –28.6 87 28 –14 58 –29.1 88 –43.8 117 –78.3 –44.3 118–127 Mute 29 –14.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 50: DAC_R1 to HPLOUT Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 DESCRIPTION D6–D0 R/W 000 0000 BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPLOUT.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.
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TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 86: LEFT_LOP/M Output Level Control Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 DESCRIPTION LEFT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.
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TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Table 9.36. Page 0/Register 101: Clock Register BIT D7–D1 D0 READ/ WRITE R R/W RESET VALUE 0000 000 0 DESCRIPTION Reserved. Write only zeros to these bits.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Page 0/Register 104: Left AGC New Programmable Decay Time Register (1) BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R/W 00 D4–D2 R/W 000 D1–D0 R/W 00 (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Left AGC is generated from register 26.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 106: Right AGC New Programmable Decay Time Register (1) BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R/W 00 D4–D2 R/W 000 D1–D0 R/W 00 (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the right AGC is generated from register 29.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down Register (1) BIT (1) D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 D4 R/W R/W 0 0 D3 D2 R/W R/W 0 0 D1 D0 R/W R/W 0 0 DESCRIPTION Reserved. Only write a 0 to this bit.
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TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.com Page 1/Register 26: Left Channel De-Emphasis Filter D1 Coefficient LSB Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0111 1110 DESCRIPTION Left Channel De-Emphasis Filter D1 Coefficient LSB.
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TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 1/Register 50: Right Channel De-Emphasis Filter N1 Coefficient LSB Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0010 1101 DESCRIPTION Right Channel De-Emphasis Filter N1 Coefficient LSB.
TLV320AIC3105 SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008......................................................................................................................................... www.ti.
TLV320AIC3105 www.ti.com......................................................................................................................................... SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 1/Register 75: Right Channel ADC High-Pass Filter D1 Coefficient MSB Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0101 0011 DESCRIPTION Right Channel ADC High-Pass Filter D1 Coefficient MSB.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3105IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3105IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3105IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3105IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TLV320AIC3105IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3105IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC3105IRHBT VQFN RHB 32 250 210.0 185.0 35.
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