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APPLICATIONS

DESCRIPTION

TLV320AIC3106

www.ti.com

........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008

LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

• Power Supplies:

• Stereo Audio DAC – Analog: 2.7 V – 3.6 V.

– 102-dBA Signal-to-Noise Ratio – Digital Core: 1.65 V – 1.95 V

– 16/20/24/32-Bit Data – Digital I/O: 1.1 V – 3.6 V

– Supports Rates From 8 kHz to 96 kHz • Packages: 5-mm × 5-mm 80-VFBGA;

7-mm × 7-mm 48-QFN

– 3D/Bass/Treble/EQ/De-Emphasis Effects

– Flexible Power Saving Modes and

Performance are Available

• Digital Cameras

• Stereo Audio ADC

• Smart Cellular Phones

– 92-dBA Signal-to-Noise Ratio

– Supports Rates From 8 kHz to 96 kHz

– Digital Signal Processing and Noise

The TLV320AIC3106 is a low-power stereo audio

Filtering Available During Record

codec with stereo headphone amplifier, as well as

• Ten Audio Input Pins

multiple inputs and outputs programmable in

single-ended or fully differential configurations.

– Programmable in Single-Ended or Fully

Extensive register-based power control is included,

Differential Configurations

enabling stereo 48-kHz DAC playback as low as 15

– 3-State Capability for Floating Input

mW from a 3.3-V analog supply, making it ideal for

Configurations

portable battery-powered audio and telephony

applications.

• Seven Audio Output Drivers

– Stereo Fully Differential or Single-Ended

The record path of the TLV320AIC3106 contains

Headphone Drivers

integrated microphone bias, digitally controlled stereo

microphone preamplifier, and automatic gain control

– Fully Differential Stereo Line Outputs

(AGC), with mix/mux capability among the multiple

– Fully Differential Mono Output

analog inputs. Programmable filters are available

• Low Power: 15-mW Stereo 48-kHz Playback

during record which can remove audible noise that

With 3.3-V Analog Supply

can occur during optical zooming in digital cameras.

The playback path includes mix/mux capability from

• Ultralow-Power Mode with Passive Analog

the stereo DAC and selected inputs, through

Bypass

programmable volume controls, to the various

• Programmable Input/Output Analog Gains

outputs.

• Automatic Gain Control (AGC) for Record

The TLV320AIC3106 contains four high-power output

• Programmable Microphone Bias Level

drivers as well as three fully differential output drivers.

• Programmable PLL for Flexible Clock

The high-power output drivers are capable of driving

a variety of load configurations, including up to four

Generation

channels of single-ended 16- Ω headphones using

• Control Bus Selectable SPI or I

ac-coupling capacitors, or stereo 16- Ω headphones in

• Audio Serial Data Bus Supports I

a capacitorless output configuration.

Left/Right-Justified, DSP, and TDM Modes

• Alternate Serial PCM/I

S Data Bus for Easy

Connection to Bluetooth™ Module

• Concurrent Digital Microphone and Analog

Microphone Support Available

• Extensive Modular Power Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 MicroStar Junior is a trademark of Texas Instruments.

3 Bluetooth is a trademark of Bluetooth SIG, Inc.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (103 pages)

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TLV320AIC3106 www.ti.com........................................................................................................................................
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 WCLK DIN DOUT BCLK SIMPLIFIED BLOCK DIAGRAM LINE2LP MIC2LP / LINE2LP MIC2LM / LINE2LM + HPLOUT LINE2LM AGC DINR MIC3L / LINE3L VCM DINL DOUTL DOUTR Audio Serial Bus Interface HPLCOM + SW-D2 LINE1LP MIC1LP / LINE1LP MIC1LM / LINE1LM PGA 0/+59.5dB 0.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com PIN ASSIGNMENTS 1 12 13 48 J H G F E D C B 37 24 A 25 36 1 2 3 4 5 6 7 8 9 5x5mm 80−Ball BGA Package (Bottom View) 48−lead QFN Package (Bottom View) (Not to scale) Solder the QFN thermal pad to the ground plane (DRVSS).
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TJ Max (2) VALUE UNIT AVDD_DAC to AVSS_DAC, DRVDD to DRVSS, AVSS_ADC –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD_DAC to DRVDD –0.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) AVDD_DAC, DRVDD (1) Analog supply voltage DVDD (1) IOVDD VI (1) Digital core supply voltage Digital I/O supply voltage MIN NOM MAX 2.7 3.3 3.6 V 1.65 1.8 1.95 V 1.8 3.6 1.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MICROPHONE BIAS Programmable setting = 2.0 Bias voltage Programmable setting = 2.5 2.0 2.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC DIGITAL INTERPOLATION – FILTER fS = 48 ksps Pass band 0 Pass-band ripple 0.45 fS ±0.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs HEADPHONE OUT POWER SIGNAL-TO-NOISE RATIO vs ADC PGA SETTING 45 0 2.7 VDD_CM 1.35_LDAC 40 3.6 VDD_CM 1.8_LDAC -20 SNR - Signal-To-Noise - dB THD - Total Harmonic Distortion - dB -10 3.3 VDD_CM1.65_LDAC 2.7 VDD_CM 1.35_RDAC -30 -40 3.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) LEFT DAC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 4096 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 f - Frequency - kHz 13 14 15 16 17 18 19 20 Figure 9.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) RIGHT ADC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 2048 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 13 f - Frequency - kHz Figure 12.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD I2C ADDRESS Rp Multimedia DBB / Processor Modem MFP1 MFP2 MFP0 GPIO1 GPIO2 MFP3 DIN DOUT WCLK BCLK MCLK SCL SDA RESET Rp AVDD (2.7V−3.6V) MICBIAS AVDD_ADC MIC3L 1 kΩ 0.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 OVERVIEW The TLV320AIC3106 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com SS SCLK MOSI Hi-Z RA(6) RA(5) RA(0) 7-bit Register Address MISO Hi-Z Don’t Care Read Hi-Z 8-bit Register Data D(7) D(6) D(0) Hi-Z Figure 15.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 After this write, it is recommended the user also read back the page control register, to safely ensure the change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access registers in page 1.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com SDA tHD-STA ³ 0.9 ms SCL tSU-STA ³ 0.9 ms tSU-STO ³ 0.9 ms tHD-STA ³ 0.9 ms S Sr P S T0114-02 2 Figure 16. I C Interface Timing I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it will receive a not−acknowledge because no device is present at that address to pull the line LOW.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com WCLK GPIO1 GPIO2 BCLK DIN DOUT MFP3 Audio Serial Data Bus Figure 19.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com n-1 n-2 n-3 n-1 n-2 n-3 Figure 22. Left-Justified Serial Data Bus Mode Operation I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 1/fs WCLK BCLK Right Channel Left Channel SDIN/SDOUT n–1 n–2 n–3 n–4 LSB MSB 2 1 0 n–1 n–2 n–3 2 LSB MSB 1 0 n–1 LSB T0152-01 Figure 24.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com DSP Mode word clock bit clock data in/out N-1 N-2 1 Left Channel Data offset 0 N-1 N-2 1 0 Right Channel Data Left Justified Mode word clock bit clock data in/out N-1 offset N-2 1 Left Channel Data 0 N-1 offset N-2 1 0 Right Channel Data Figure 25.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 MCLK BCLK GPIO2 CLKDIV_CLKIN PLL_CLKIN CLKDIV_IN Q=2,3,…..,16,17 PLL_IN K = J.D J = 1,2,3,…..,62,63 D= 0000,0001,….,9998,9999 R= 1,2,3,4,….,15,16 P= 1,2,….
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com fS(ref) = (PLLCLK_IN × K × R) / (2048 × P), where P = 1, 2, 3,…, 8 R = 1, 2, …, 16 K = J.D J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4 P, R, J, and D are register programmable.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 8.192 1 1 12 0 48000.00 0.0000 12.0 1 1 8 1920 48000.00 0.0000 13.0 1 1 7 5618 47999.71 –0.0006 16.0 1 1 6 1440 48000.00 0.0000 19.2 1 1 5 1200 48000.00 0.0000 19.68 1 1 4 9951 47999.79 –0.0004 48.0 4 1 8 1920 48000.00 0.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com STEREO AUDIO ADC HIGH-PASS FILTER Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The TLV320AIC3106 has a programmable first-order high-pass filter which can be used for this purpose.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 AUTOMATIC GAIN CONTROL (AGC) An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired).
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 filter is designed to maintain at least 65-dB rejection of images that land below 7.455 fS.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com a programmable output common-mode level, which can be set by register programming to a level most appropriate to the actual supply range used by a particular customer. The output common-mode level can be varied among four different values, ranging from 1.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 GAIN=0,−1.5,−3,..,−12dB,MUTE LINE1LP LINE1LM GAIN=0,−1.5,−3,..,−12dB, MUTE LINE2LP TO LEFT ADC LINE2LM PGA GAIN=0,−1.5,−3,..,−12dB,MUTE LINE1RP LINE1RM Figure 31.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the ADC PGAs is also possible in this mode.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described above, the TLV320AIC3106 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the output drivers.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC3106 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 34 and Figure 35.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com LINE2L/MIC2L 0dB to -78dB LINE2R/MIC2R 0dB to -78dB PGA_L 0dB to -78dB + PGA_R 0dB to -78dB DAC_L1 0dB to -78dB DAC_R1 0dB to -78dB Figure 35.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 The output stage architecture leading to the high power output drivers is shown in Figure 36, with the volume control and mixing blocks being effectively identical to that shown in Figure 35.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com When these output drivers are powered down, they can be placed into a variety of output conditions based on register programming. If lowest power operation is desired, then the outputs can be placed into a 3-state condition, and all power to the output stage is removed.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 AVDD Stereo g s MICBIAS MICDET s To Detection block MIC3(L/R) Cellular g m s HPLOUT Stereo + g Cellular m s s HPROUT m = mic HPRCOM s = earspeaker To detection block 1.35 HPLCOM g = ground/midbias Figure 37.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com This switch closes when MICDET jack is removed To Detection block HPLOUT HPLCOM HPRCOM HPROUT Figure 39. Configuration of Device for Jack Detection Using a Fully Differential Stereo Headphone Output Connection GENERAL-PURPOSE I/O TLV320AIC3106 has two dedicated pins for general-purpose I/O.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 Page 0 / Register 26: D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 BIT (1) Left AGC Control Register A DESCRIPTION Left AGC Enable 0: Left AGC is disabled 1: Left AGC is enabled Left AGC Target Level 000: Left AGC target level = –5.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 Page 0 / Register 32: BIT D7–D0 READ/ WRITE R RESET VALUE 0000 0000 DESCRIPTION Left Channel Gain Applied by AGC Algorithm 1110 1000: Gain = –12 dB 1110 1001: Gain = –11.5 dB 1110 1010: Gain = –11 dB … 0000 0000: Gain = 0 dB 0000 0001: Gain = 0.5 dB … 0111 0110: Gain = 59 dB 0111 0111: Gain = 59.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 35: D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 BIT (1) Right AGC Noise Gate Debounce Register DESCRIPTION Right AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 40: D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D4 R/W 00 D3–D2 R/W 00 D1–D0 R/W 00 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D4 R/W 00 D3–D2 D1–D0 R/W R/W 00 00 BIT DESCRIPTION Output Common-Mode Voltage Control 00: Output common-mode voltage = 1.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 72: D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 BIT DESCRIPTION HPRCOM Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 93: D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 BIT RIGHT_LOP/M Output Level Control Register DESCRIPTION RIGHT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ..
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 99: D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R 0 D1 R/W 0 D0 R 0 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5 R/W 0 D4 R 0 D3–D2 R/W 00 D1 R/W 0 D0 R 0 BIT DESCRIPTION GPIO2 Output Control 0000: GPIO2 is disabled 0001: Reserved. Do not use.
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TLV320AIC3106 SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 103: D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R/W 00 D4–D2 R/W 000 D1–D0 R/W 00 BIT DESCRIPTION Attack Time Register Selection 0: Attack time for the left AGC is generated from register 26. 1: Attack time for the left AGC is generated from this register.
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TLV320AIC3106 www.ti.com........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 Page 0 / Register 105: D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R/W 00 D4–D2 R/W 000 D1–D0 R/W 00 BIT DESCRIPTION Attack Time Register Selection 0: Attack time for the Right AGC is generated from Register 29. 1: Attack time for the Right AGC is generated from this Register.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3106IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TLV320AIC3106IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3106IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 TLV320AIC3106IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.