Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsTLV320AIC3107IRSBT

FEATURES

APPLICATIONS

DESCRIPTION

TLV320AIC3107

www.ti.com

.............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009

LOW-POWER STEREO CODEC WITH

INTEGRATED MONO CLASS-D SPEAKER AMPLIFIER

• Extensive Modular Power Control

• Stereo CODEC with Integrated Mono Class-D • Power Supplies:

Amplifier

– Speaker Amp: 2.7 V – 5.5 V

• High Performance Audio DAC

– Analog: 2.7 V – 3.6 V.

– 97 dBA Signal-to-Noise Ratio

– Digital Core: 1.525 V – 1.95 V

(Single Ended)

– Digital I/O: 1.1 V – 3.6 V

– 16/20/24/32-Bit Data

• Packages: 5 × 5 mm 40-QFN, 0.4 mm Pitch

– Supports Sample Rates From 8 kHz to

• 3.5 × 3 mm 42-WCSP, 0.5 mm Pitch

96 kHz

– 3D/Bass/Treble/EQ/De-Emphasis Effects

– Flexible Power Saving Modes and

• Cellular Handsets

Performance are Available

• Digital Cameras

• High Performance Audio ADC

• Portable Media Players

– 92 dBA Signal-to-Noise Ratio

• General Portable Audio Equipment

– Supports Rates From 8 kHz to 96 kHz

– Digital Signal Processing and Noise

Filtering Available During Record

The TLV320AIC3107 is a low power stereo audio

codec with stereo headphone amplifier, and mono

• Seven Audio Input Pins

class-D speaker driver, as well as multiple inputs and

– Programmable as 6 Single-Ended or 3 Fully

outputs programmable in single-ended or fully

Differential Inputs

differential configurations. Extensive register-based

– Capability for Floating Input Configurations

power control is included, enabling stereo 48-kHz

DAC playback as low as 15 mW from a 3.3-V analog

• Multiple Audio Output Drivers

supply, making it ideal for portable battery-powered

– Mono Fully Differential or Stereo

audio and telephony applications.

Single-Ended Headphone Drivers

The record path of the TLV320AIC3107 contains

– Single-Ended Stereo Line Outputs

integrated microphone bias, digitally controlled stereo

• Mono 1W Class-D BTL 8 Ω Speaker Driver

microphone preamplifier, and automatic gain control

(AGC), with mix/mux capability among the multiple

• Low Power Consumption: 15-mW Stereo

analog inputs. Programmable filters are available

48-kHz Playback With 3.3-V Analog Supply

during record which can remove audible noise that

• Ultra-Low Power Mode with Passive Analog

can occur during optical zooming in digital cameras.

Bypass

The playback path includes mix/mux capability from

• Programmable Input/Output Analog Gains

the stereo DAC and selected inputs, through

programmable volume controls, to the various

• Automatic Gain Control (AGC) for Record

outputs.

• Programmable Microphone Bias Level

The TLV320AIC3107 contains three high-power

• Programmable PLL for Flexible Clock

output drivers as well as two single-ended line output

Generation

drivers, and a differential class-D output driver.

• I

C™ Control Bus

• Audio Serial Data Bus Supports I

Left/Right-Justified, DSP, and TDM Modes

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 I2C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (100 pages)

PAGE 1
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 2
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 4
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 5
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 6
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT AVDD_DAC to AVSS_DAC, DRVDD to DRVSS, AVSS_ADC –0.3 to 3.9 V SPVDD to SPVSS –0.3 to 6.0 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.
PAGE 7
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.
PAGE 8
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 2.3 2.5 MAX UNIT MICROPHONE BIAS Programmable setting = 2.
PAGE 9
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.
PAGE 10
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, SPVDD = 5V, DVDD = 1.
PAGE 11
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
PAGE 12
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com All specifications at 25°C, DVDD = 1.8 V WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
PAGE 13
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 All specifications at 25°C, DVDD = 1.8 V WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
PAGE 14
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com All specifications at 25°C, DVDD = 1.8 V WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
PAGE 15
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs HEADPHONE OUT POWER SIGNAL-TO-NOISE RATIO vs ADC PGA SETTING 45 0 2.7 VDD_CM 1.35_LDAC 40 3.6 VDD_CM 1.8_LDAC -20 SNR - Signal-To-Noise - dB THD - Total Harmonic Distortion - dB -10 3.3 VDD_CM1.65_LDAC 2.7 VDD_CM 1.35_RDAC -30 -40 3.
PAGE 16
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) LEFT DAC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 4096 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 f - Frequency - kHz 13 14 15 16 17 18 19 20 Figure 9.
PAGE 17
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS (continued) RIGHT ADC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 2048 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 13 f - Frequency - kHz Figure 12.
PAGE 18
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD Multimedia Rp Processor Rp AVDD (2.7V-3.6V) GPIO1 DOUT DIN BCLK WCLK MCLK SDA /RESET SCL AVDD_ADC AVDD_DAC DRVDD DRVDD MICBIAS 1k W 0.1 mF IOVDD (1.1-3.3V) A IOVDD A LINE1LP 1.525-1.95V 0.
PAGE 19
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 OVERVIEW The TLV320AIC3107 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
PAGE 20
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master.
PAGE 21
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 22
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface will be put into a 3-state output condition.
PAGE 23
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 n-1 n-2 n-3 n-1 n-2 n-3 Figure 20. I2S Serial Data Bus Mode Operation DSP MODE In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data.
PAGE 24
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com DSP Mode word clock bit clock data in/out N-1 N-2 1 Left Channel Data offset 0 N-1 N-2 1 0 Right Channel Data Left Justified Mode word clock bit clock data in/out N-1 offset N-2 1 Left Channel Data 0 N-1 offset N-2 1 0 Right Channel Data Figure 22.
PAGE 25
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 MCLK BCLK PLL_CLKIN CLKDIV_CLKIN CLKDIV_IN PLL_IN Q=2,3,…..,16,17 K = J.D J = 1,2,3,…..,62,63 D= 0000,0001,….,9998,9999 R= 1,2,3,4,….,15,16 P= 1,2,….
PAGE 26
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com K = J.D J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4 P, R, J, and D are register programmable.
PAGE 27
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 16.0 1 1 6 1440 48000.00 0.0000 19.2 1 1 5 1200 48000.00 0.0000 19.68 1 1 4 9951 47999.79 –0.0004 48.0 4 1 8 1920 48000.00 0.0000 The 'AIC3107 can also output a separate clock on the GPIO1 pin.
PAGE 28
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com H(z) + N0 ) N1 z *1 32768 * D1 z *1 (1) Programming the Left channel is done by writing to Page 1, Registers 65-70, and the right channel is programmed by writing to Page 1, Registers 71-76.
PAGE 29
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine tuned for any particular application.
PAGE 30
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Input Signal Target Level Output Signal AGC Gain Decay Time Attack Time Figure 25. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode.
PAGE 31
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing.
PAGE 32
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications.
PAGE 33
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 DIGITAL INTERPOLATION FILTER The digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter stages.
PAGE 34
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com ANALOG OUTPUT COMMON-MODE ADJUSTMENT The output common-mode voltage and output range of the analog output are determined by an internal bandgap reference, in contrast to other codecs that may use a divided version of the supply.
PAGE 35
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 AUDIO ANALOG INPUTS LINE1LP 0dB to -18dB in 0.5dB Steps LINE2LP 0dB, -6dB, or -12dB LINE1RP 0dB to -18dB in 0.5dB Steps MIC3L/LINE 1RM MIC3L 0dB to -18dB in 0.5dB Steps MIC3R MIC3R/LINE2RM Left ADC 0dB to -18dB in 0.5dB Steps LINE1LM PDWN MICDET/LINE1LM 0dB to -18dB in 0.
PAGE 36
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com LINE1RP 0dB to -18dB in 0.5dB Steps LINE2RP/LINE2LM 0dB, -6dB, or -12dB LINE1LP 0dB to -18dB in 0.5dB Steps MIC3L/LINE 1RM MIC3L 0dB to -18dB in 0.5dB Steps MIC3R/LINE2RM MIC3R Right ADC 0dB to -18dB in 0.5dB Steps LINE1RM PDWN 0dB to -18dB in 0.
PAGE 37
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 The TLV320AIC3107 includes seven analog audio input pins, which can be configured as up to three fully-differential pair plus one single-ended audio inputs, or up to six single-ended audio inputs. .
PAGE 38
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the ADC PGAs is also possible in this mode.
PAGE 39
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described above, the TLV320AIC3107 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the output drivers.
PAGE 40
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 41
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ANALOG LINE OUTPUT DRIVERS The TLV320AIC3107 has two single-ended line output drivers, each capable of driving a 10-kΩ load. The output stage design leading to the fully differential line output drivers is shown in Figure 33 and Figure 34.
PAGE 42
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com LINE2L 0dB to -78dB LINE2R 0dB to -78dB PGA_L 0dB to -78dB + PGA_R 0dB to -78dB DAC_L1 0dB to -78dB DAC_R1 0dB to -78dB Figure 34.
PAGE 43
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 The output stage architecture leading to the high power output drivers is shown in Figure 35, with the volume control and mixing blocks being effectively identical to that shown in Figure 34.
PAGE 44
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com The device includes a further option that falls between the other two – while it requires less power drawn while the output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the bandgap reference is kept alive.
PAGE 45
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Stereo g s MICBIAS MICDET s AVDD To Detection block MIC3(L/R) Cellular g m s HPLOUT Stereo + Cellular g m s s HPROUT m = mic s = earspeaker g = ground/midbias Figure 37.
PAGE 46
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com CLASS-D SPEAKER DRIVER Differential Class-D speaker outputs are available on the SPOP and SPOM pins as shown in Figure 39. The integrated Class-D speaker amplifier can drive a one Watt audio signal into a differential 8-Ω load.
PAGE 47
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 GENERAL PURPOSE I/O 'AIC3107 has a dedicated pin for General Purpose IO. This pin can be used to read status of external signals through register read when configured as General Purpose Input. When configured as General Purpose Output , this pin can also drive logic high or low.
PAGE 48
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 2: BIT Codec Sample Rate Select Register D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3-D0 R/W 0000 DESCRIPTION ADC Sample Rate Select 0000: ADC Fs = Fsref/1 0001: ADC Fs = Fsref/1.5 0010: ADC Fs = Fsref/2 0011: ADC Fs = Fsref/2.
PAGE 49
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 50
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 51
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 52
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 53
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 54
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 55
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 56
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 57
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 58
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 26: BIT (1) D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 DESCRIPTION Left AGC Enable 0: Left AGC is disabled 1: Left AGC is enabled Left AGC Target Level 000: Left AGC target level = –5.
PAGE 59
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 60
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 32: BIT D7–D0 READ/ WRITE R RESET VALUE 00000000 DESCRIPTION Left Channel Gain Applied by AGC Algorithm 11101000: Gain = –12.0 dB 11101001: Gain = –11.5 dB 11101010: Gain = –11.0 dB … 00000000: Gain = 0.0 dB 00000001: Gain = +0.5 dB … 01110110: Gain = +59.
PAGE 61
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Page 0 / Register 35: BIT (1) D7–D3 READ/ WRITE R/W RESET VALUE 00000 D2–D0 R/W 000 Right AGC Noise Gate Debounce Register DESCRIPTION Right AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled.
PAGE 62
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 63
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 64
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 44: BIT D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 0000000 Right DAC Digital Volume Control Register DESCRIPTION Right DAC Digital Mute 0: The right DAC channel is not muted 1: The right DAC channel is muted Right DAC Digital Volume Control Setting 0000000: Gain = 0.
PAGE 65
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Table 5. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 27 -13.5 57 -28.6 87 28 -14.0 58 -29.1 88 29 -14.5 59 -29.6 89 -44.
PAGE 66
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 67
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 68
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 69
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 70
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 72: BIT D7–D 0 READ/ WRITE R RESET VALUE 00000000 Reserved. Do not write to this register.
PAGE 71
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 72
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 73
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Page 0 / Register 86: BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 DESCRIPTION LEFT_LOP Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
PAGE 74
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 75
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 76
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 77
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 78
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 99: BIT D7–D0 READ/ WRITE R RESET VALUE 00000000 READ/ WRITE R RESET VALUE 00000000 DESCRIPTION Reserved. Do not write to this register.
PAGE 79
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Page 0 / Register 104: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D5 R/W 00 D4-D2 R/W 000 D1-D0 R/W 00 (1) Left AGC Programmable Decay Time Register (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Left AGC is generated from Register 26.
PAGE 80
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com Page 0 / Register 106: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D5 R/W 00 D4-D2 R/W 000 D1-D0 R/W 00 (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Right AGC is generated from Register 29. 1: Decay time for the Right AGC is generated from this Register.
PAGE 81
TLV320AIC3107 www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Page 0 / Register 108: BIT (1) D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 D4 R/W R/W 0 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 Passive Analog Signal Bypass Selection During Powerdown Register (1) DESCRIPTION Reserved. Write only zero to this register bit.
PAGE 82
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 83
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 84
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 85
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 86
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 87
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 88
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 89
TLV320AIC3107 www.ti.com ..............................................................................................................................................
PAGE 90
TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.
PAGE 91
37 38 WCLK BCLK DOUT DIN MCLK 34 35 36 TLV320AIC3107IRSB Functional Block Diagram with Registers (ver. 0.95) Sample Rate Select = (R2) LINE2LP LINE2L PGA 0/+59.5dB 0.5dB steps SW-D1 LB2 (P1:R1-R6, R13-R16) (P1:R7-R12, R17-R20) (R12,D7-6) (R107,D7) (P1:R65-R70) (R15) DAC_L1 1st Ord deemp 0 1 DAC L DAC_L2 DAC_L3 (P1:R21-R16) PGA_L + L Ch P1:R53-R54 + + LB1 - + 1st Ord LB2 + Atten - + + 1st Ord RB2 LINE1R (R21, Gain: R22) PGA 0/+59.5dB 0.5dB steps + 0 to -12 dB 1.
PAGE 92
PACKAGE OPTION ADDENDUM www.ti.
PAGE 93
PACKAGE OPTION ADDENDUM www.ti.
PAGE 94
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3107IRSBR WQFN RSB 40 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3107IRSBT WQFN RSB 40 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PAGE 95
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3107IRSBR WQFN RSB 40 3000 367.0 367.0 35.0 TLV320AIC3107IRSBT WQFN RSB 40 250 210.0 185.0 35.
PAGE 96
PAGE 97
PAGE 98
PAGE 99
D: Max = 3.563 mm, Min =3.503 mm E: Max = 3.376 mm, Min =3.
PAGE 100
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.