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TLV320AIC3110

www.ti.com

SLAS647B –DECEMBER 2009–REVISED MAY 2012

Low-Power Audio Codec With Audio Processing

and Stereo Class-D Speaker Amplifier

Check for Samples: TLV320AIC3110

1 INTRODUCTION

Key-Clicks

1.1 Features

• Integrated PLL Used for Programmable Digital

123

• Stereo Audio DAC With 95-dB SNR

Audio Processor

• Mono Audio ADC With 91-dB SNR

• I

S, Left-Justified, Right-Justified, DSP, and

• Supports 8-kHz to 192-kHz Separate DAC and

TDM Audio Interfaces

ADC Sample Rates

• I

C Control With Register Auto-Increment

• Stereo 1.29-W Class-D BTL 8-Ω Speaker Driver

• Full Power-Down Control

With Direct Battery Connection

• Power Supplies:

• One Differential and Three Single-Ended Inputs

– Analog: 2.7 V–3.6 V

With Mixing and Level Controls

– Digital Core: 1.65 V–1.95 V

• Microphone With Bias, Preamp PGA, and AGC

– Digital I/O: 1.1 V–3.6 V

• Built-in Digital Audio Processing Blocks (PRB)

– Class-D: 2.7 V–5.5 V (SPLVDD and SPRVDD

With User-Programmable Biquad, FIR Filters,

≥ AVDD)

and DRC

• 5-mm × 5-mm 32-QFN Package

• Digital Mixing Capability

• Programmable Digital Audio Processor for

1.2 Applications

Bass Boost/Treble/EQ With up to Five Biquads

for Record and up to Six Biquads for Playback

• Portable Audio Devices

• Pin Control or Register Control for Digital-

• Mobile Internet Devices

Playback Volume-Control Settings

• e-Books

• Digital Sine-Wave Generator for Beeps and

1.3 Description

The TLV320AIC3110 is a low-power, highly integrated, high-performance codec which supports stereo

audio DAC, and mono audio ADC.

The TLV320AIC3110 features a high-performance audio codec with 24-bit stereo playback and monaural

record functionality. The device integrates several analog features, such as a microphone interface,

headphone drivers, and speaker drivers. The digital audio data format is programmable to work with

popular audio standard protocols (I

S, left/right-justified) in master, slave, DSP, and TDM modes. Bass

boost, treble, or EQ can be supported by the programmable digital-signal processing blocks (PRB). An on-

chip PLL provides the high-speed clock needed by the digital-signal processing block. The volume level

can be controlled either by pin control or by register control. The audio functions are controlled using the

C serial bus.

The TLV320AIC3110 has a programmable digital sine-wave generator and is available in a 32-pin QFN

package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MATLAB is a trademark of The MathWorks, Inc.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (127 pages)

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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Low-Power Audio Codec With Audio Processing and Stereo Class-D Speaker Amplifier Check for Samples: TLV320AIC3110 1 INTRODUCTION 1.1 Features • Stereo Audio DAC With 95-dB SNR • Mono Audio ADC With 91-dB SNR • Supports 8-kHz to 192-kHz Separate DAC and ADC Sample Rates • Stereo 1.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 NOTE This data manual is designed using PDF document-viewing features that allow quick access to information. For example, performing a global search on "page 0 / register 27" produces all references to this page and register in a list. This makes is easy to traverse the list and find all information related to a page and register. Note that the search string must be of the indicated format.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320AIC3110 QFN-32 RHB –40°C to 85°C 2.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 3.2 www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM (2) 2.7 3.3 3.6 Referenced to DVSS(2) 1.65 1.8 1.95 Referenced to HPVSS(2) 2.7 3.3 3.6 Referenced to SPLVSS(2) 2.7 SPRVDD (1) Referenced to SPRVSS(2) 2.7 IOVDD Referenced to IOVSS(2) 1.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD = SPRVDD = 3.6 V; DVDD = 1.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD = SPRVDD = 3.6 V; DVDD = 1.8 V; fS (audio) = 48 kHz; CODEC_CLKIN = 256 × fS; PLL = Off; VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Output to Class-D Speaker Output, Load = 8 Ω (Differential), 50 pF SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.
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TLV320AIC3110 www.ti.com 3.4 3.4.1 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Timing Characteristics I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 3.4.2 www.ti.com I2S/LJF/RJF Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization.
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TLV320AIC3110 www.ti.com 3.4.3 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK td(WS) td(WS) tf BCLK tr td(DO-BCLK) DOUT tS(DI) th(DI) DIN T0146-07 IOVDD = 1.1 V MIN MAX 45 45 8 8 25 25 PARAMETER td(WS) td(DO-BCLK) ts(DI) th(DI) tr tf WCLK delay BCLK to DOUT delay DIN setup DIN hold Rise time Fall time IOVDD = 3.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 3.4.4 www.ti.com DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tS(WS) tS(WS) th(WS) th(WS) tf tL(BCLK) BCLK tr td(DO-BCLK) tH(BCLK) DOUT tS(DI) th(DI) DIN T0146-08 IOVDD = 1.
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TLV320AIC3110 www.ti.com 3.4.5 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time (repeated) START condition.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 4 TYPICAL PERFORMANCE 4.1 Audio ADC Performance H AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 20 20 AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V 0 −20 −20 −40 −40 Amplitude − dBFS Amplitude − dBFS 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 f − Frequency − kHz 10 15 G018 G019 Figure 4-1.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 AMPLITUDE vs FREQUENCY SNR vs PGA CHANNEL GAIN 0 100 AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V −10 Diff = 10k 90 −30 85 −40 80 SNR − dB Amplitude − dBFS −20 95 −50 −60 SE = 10k 70 65 −80 60 −90 55 0 50 100 150 Diff = 40k 75 −70 −100 Diff = 20k SE = 20k SE = 40k 50 −10 200 0 10 f − Frequency − kHz G028 40 50 60 70 80 G022 Figure 4-6. SNR vs.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − dB 0 HPVDD = 2.7 V CM = 1.35 V −10 −20 −30 −40 HPVDD = 3 V CM = 1.5 V −50 HPVDD = 3.3 V CM = 1.65 V −60 HPVDD = 3.6 V CM = 1.8 V −70 IOVDD = 3.3 V DVDD = 1.8 V Gain = 9 dB RL = 16 Ω −80 −90 −100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 PO − Output Power − W 0.14 G025 Figure 4-9. Headphone Output Power 4.
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TLV320AIC3110 www.ti.com 4.4 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Analog Bypass Performance H AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 20 20 AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V 0 −20 −20 −40 −40 Amplitude − dBFS Amplitude − dBFS 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 f − Frequency − kHz 10 15 20 f − Frequency − kHz G024 G027 Figure 4-12.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 5 APPLICATION INFORMATION 5.1 Typical Circuit Configuration +3.3VA SVDD 0.1 mF 22 mF 0.1 mF SPLVDD SPRVDD 0.1 mF 22 mF 0.1 mF 10 mF HPVDD AVDD SPLVSS SPRVSS 10 mF AVSS HPVSS 8W SPLP SPLM GPIO1 Speakers 8W SPRP SPRM SDA VOL/MICDET 2.2 kW MCLK MICBIAS 0.
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TLV320AIC3110 www.ti.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.2.1.5 www.ti.com Software Power Down By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit block can be controlled by writing to the appropriate control register. This approach allows the lowest power-supply current for the functionality required. However, when a block is powered down, all of the register settings are maintained as long as power is still being applied to the device. 5.2.
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TLV320AIC3110 www.ti.com 5.3.2 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A) Power consumption = 6.77 mW Table 5-3. PRB_R4 Alternative Processing Blocks, 6.77 mW Processing Block Filter Estimated Power Change (mW) PRB_R5 A 0.03 PRB_R6 A 0.03 AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B) Power consumption = 6.61 mW Table 5-4. PRB_R11 Alternative Processing Blocks, 6.61 mW 5.3.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.5 mW Table 5-6. PRB_P7 Alternative Processing Blocks, 24.5 mW 5.3.4 Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.17 PRB_P2 A 2.62 PRB_P3 A 2 PRB_P8 B 0.99 PRB_P9 B 0.5 PRB_P10 B 1.46 PRB_P11 B 0.66 PRB_P23 A 1.43 PRB_P24 A 2.69 PRB_P25 A 2.92 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.
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TLV320AIC3110 www.ti.com 5.3.5 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 22.44 mW Table 5-9. PRB_P7 Alternative Processing Blocks, 22.44 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 0.02 PRB_P2 A 0.31 PRB_P3 A 0.23 PRB_P8 B 0.28 PRB_P9 B –0.03 PRB_P10 B 0.14 PRB_P11 B 0.05 PRB_P23 A 0.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.42 mW Table 5-12. PRB_P12 Alternative Processing Blocks, 14.42 mW 5.3.7 Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.16 PRB_P5 A 0.3 PRB_P6 A 0.2 PRB_P13 B 0.15 PRB_P14 B 0.07 PRB_P15 B 0.18 PRB_P16 B 0.09 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3110 integrates a secondorder analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.4.2 www.ti.com Automatic Gain Control (AGC) The TLV320AIC3110 includes automatic gain control (AGC) for the microphone inputs. AGC can be used to maintain nominally constant output-signal amplitude when recording speech signals. This circuitry automatically adjusts the MIC PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer to or farther from the microphone.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 5-16.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 5-17.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.4.4.2 www.ti.com ADC Processing Blocks – Signal Chain Details 5.4.4.2.1 First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone Filter A AGC Gain Compen Sation st 1 Order IIR ´ To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-3. Signal Chain for PRB_R4 5.4.4.2.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.4.4.2.4 First-Order IIR, AGC, Filter B From Delta-Sigma Modulator or Digital Microphone AGC Gain Compen sation st Filter B 1 Order IIR ´ To Audio Interface To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-6. Signal Chain for PRB_R10 5.4.4.2.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 5.4.4.2.7 First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone Filter C ´ AGC Gain Compen sation st 1 Order IIR To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-9. Signal Chain for PRB_R16 5.4.4.2.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 The coefficients of these filters are each 16 bits wide, in 2s-complement format, and occupy two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF), as shown in Figure 5-12. 2 –15 2 2 –4 –1 Bit Bit Largest Positive Number: = 0.111111111111111111 = 0.999969482421875 = 1.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-19. ADC Biquad Filter Coefficients Filter Coefficient RAM Location Filter Filter Coefficient Biquad A N0 Page 4 / register 14 and page 4 / register 15 0x7FFF (decimal 1.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 M H(z) = å FIRn z-n n =0 M = 24 for PRB _ R6, PRB _ R18 M = 19 for PRB _ R12 (3) The coefficients of the FIR filters are 16-bit 2s-complement format (2 bytes each) and correspond to the ADC coefficient space as listed in Table 5-20. Note that the default (reset) coefficients are not vaild for the FIR filter. When the FIR filter is used, all applicable coefficients must be reprogrammed by the user.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-20. ADC FIR Filter Coefficients (continued) Filter Coefficient 5.4.4.4 FIlter Coefficient RAM Location Default (Reset) Values – Not Valid for the FIR Filter – Must Be Reprogrammed by User Fir20 Page 4 / register 54 0x7FFF (decimal 1.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 ADC Channel Response for Decimation Filter A (Red Line Corresponds to –73 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Frequency Normalized to fS 2 Figure 5-13. ADC Decimation Filter A, Frequency Response 5.4.4.4.2 Decimation Filter B Filter B is intended to support sampling rates up to 96 kHz at an oversampling ratio of 64. Table 5-22.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 5.4.4.4.3 Decimation Filter C Filter C along with an AOSR of 32 is specially designed for 192-ksps operation of the ADC. The pass band, which extends up to 0.11 × fS (corresponding to 21 kHz), is suited for audio applications. Table 5-23. ADC Decimation Filter C, Specifications Parameter Condition Value (Typical) Unit Filter gain from 0 to 0.11 fS 0 … 0.11 fS ±0.033 dB Filter gain from 0.28 fS to 16 fS 0.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Record - Paused Volume Ramp Down Soft Mute ADC Volume Ramp Down WAIT Time (A) Wait (A) ms For fS = 32 kHz ® Wait 10 ms (min) For fS = 48 kHz ® Wait 8 ms (min) ADC Power Down Update Digital Filter Coefficients ADC Volume Ramp Up Time (B) For fS = 32 kHz ® 10 ms For fS = 48 kHz ® 8 ms ADC Power UP Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Record - Continue F0023-02 Figure 5-16.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com D-S ADC Signal Processing Blocks DOUT DIG_MIC_IN Mono ADC CIC Filter ADC_MOD_CLK SDIN GPIO1 Figure 5-17. Digital Microphone in the TLV320AIC3110 The TLV320AIC3110 outputs internal clock ADC_MOD_CLK on the GPIO1 pin (page 0 / register 51, bits D5–D2 = 1010). This clock can be connected to the external digital microphone device. The single-bit output of the external digital microphone device can be connected to the DIN pin.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Mode B To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B, a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102, bits D4–D0. The nature of the filter is given in Table 5-24. Table 5-24. DC Measurement Bandwidth Settings D:Page 0 / register 102, Bits D4–D0 –3 dB BW (kHz) –0.5 dB BW (kHz) 1 688.44 236.5 2 275.97 96.334 3 127.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320AIC3110 allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 / register 14.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 5-25. Overview – DAC Predefined Processing Blocks Processing Block No.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 5.5.1.2.3 Six Biquads, First-Order IIR, Filter A or B BiQuad A IIR from Interface BiQuad B BiQuad C BiQuad D BiQuad E Interp. Filter A,B BiQuad F to Modulator ´ Digital Volume Ctrl Figure 5-21. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16 5.5.1.2.4 IIR, Filter B or C Interp. Filter B,C IIR from Interface to Modulator ´ Digital Volume Ctrl Figure 5-22. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20 5.5.1.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.5.1.2.8 Four Biquads, First-Order IIR, Filter C IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to modulator Digital Volume Ctrl Figure 5-26. Signal Chain for PRB_P19 and PRB_P22 5.5.1.2.9 Two Biquads, 3D, Filter A From LeftChannel Interface + Biquad BL + Biquad CL Interp.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com 5.5.1.2.10 Five Biquads, DRC, 3D, Filter A IIR from Left Left Channel Interface + BiQuad CL BiQuad BL + BiQuad DL BiQuad EL BiQuad FL Interp. Filter A to Modulator ´ + HPF + BiQuad AL + - Digital Volume Ctrl DRC 3D PGA BiQuad AR from Right Channel Interface IIR Right + BiQuad BR + BiQuad CR BiQuad DR BiQuad ER BiQuad FR HPF Interp. Filter A to Modulator ´ Digital Volume Ctrl DRC Figure 5-28.
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TLV320AIC3110 www.ti.com 5.5.1.3 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 DAC User-Programmable Filters Depending on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-27. DAC IIR Filter Coefficients Filter DAC Coefficient, Left Channel Filter Coefficient First-order IIR DAC Coefficient, Right Channel Default (Reset) Values N0 Page 9 / register 2 and page 9 / register 3 Page 9 / register 8 and page 9 / 0x7FFF (decimal 1.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 5-28. DAC Biquad Filter Coefficients (continued) Filter Coefficient Biquad D Biquad E Biquad F 5.5.1.4 Left DAC Channel Right DAC Channel Default (Reset) Values N0 Page 8 / register 32 and page 8 / register 33 Page 8 / register 96 and page 8 / register 97 0x7FFF (decimal 1.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com DAC Channel Response for Interpolation Filter A (Red Line Corresponds to –65 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 1 2 5 6 3 4 Frequency Normalized to fS 7 Figure 5-30. Frequency Response of DAC Interpolation Filter A 5.5.1.4.2 Interpolation Filter B Filter B is specifically designed for an fS up to 96 ksps. Thus, the flat pass-band region easily covers the required audio band of 0 kHz–20 kHz. Table 5-30.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.5.1.4.3 Interpolation Filter C Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × fS (corresponds to 80 kHz), more than sufficient for audio applications. DAC Channel Response for Interpolation Filter C (Red Line Corresponds to –43 dB) 0 Magnitude – dB –10 –20 –30 –40 –50 –60 –70 0 0.2 0.4 0.6 0.8 1 1.2 Frequency Normalized to fS 1.4 Figure 5-32.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.5.3 www.ti.com Volume-Control Pin The range of voltages used by the 7-bit SAR ADC is shown in the Electrical Characteristics table. The volume-control pin is not enabled by default but it can be enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 The VOL/MICDET pin connection and functionality are shown in Figure 5-33. 24 dB to Mute Digital DAC_L D-S DAC Vol Ctl Processing Blocks 24 dB to Mute AVDD Digital VREF IN R1 AVDD VOL/ MICDET DAC_R D-S DAC Vol Ctl Processing Blocks 18 dB to Mute P1 7- Bit ADC R2 CVOL Tone Generator and Mixer Are NOT Shown 24 dB to Mute Volume Level Register Controlled AVSS B0210-08 Figure 5-33.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is concentrated in the low-frequency region of the input signal.
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TLV320AIC3110 www.ti.com 5.5.4.2 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 DRC Hysteresis DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be programmed to represent values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled, or the enabled DRC to become disabled.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Script #Go to Page 0 w 30 00 00 #DAC => 12 db gain left w 30 41 18 #DAC => 12 db gain right w 30 42 18 #DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB w 30 44 7F #DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs' w 30 45 00 #Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame w 30 46 B6 #Go to Page 9 w 30 00 09 #DRC HPF w 30 0E 7F AB 80 55 7F 56 #DRC LPF W 30 14 00 11 00 11 7F DE 5.5.4.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 The TLV320AIC3110 also provides feedback to the user when a button press or a headset insertion/removal event is detected through register-readable flags as well as an interrupt on the I/O pins. The value in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion. Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.5.5 www.ti.com Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) A special algorithm has been included in digital signal-processing block PRB_P25 for generating a digital sine-wave signal that is sent to the DAC. The digital sine-wave generator is also referred to as the beep generator in this document. This functionality is intended for generating key-click sounds or beeps for user feedback.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused MSBs must be written as 0s. 3. For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs must be written as 0s. Following the beep volume control is a digital mixer that mixes in a playback data stream whose level has already been set by the DAC volume control.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Play - Paused Volume Ramp Down Soft Mute Wait (A) ms DAC Volume Ramp Down WAIT Time (A) For fS = 32 kHz ® Wait 25 ms (min) DAC Power Down Update Digital Filter Coefficients For fS = 48 kHz ® Wait 20 ms (min) DAC Volume Ramp Up Time (B) For fS = 32 kHz ® 25 ms For fS = 48 kHz ® 20 ms DAC Power UP Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Play - Continue F0024-02 Figure 5-35.
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TLV320AIC3110 www.ti.com 5.5.9 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Analog Audio Routing The TLV320AIC3110 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels. The TLV320AIC3110 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-38. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) (1) Register Value (D6–D0) (1) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) 0 0.0 30 –15.0 60 –30.1 90 –45.2 1 –0.5 31 –15.5 61 –30.6 91 –45.8 2 –1.0 32 –16.0 62 –31.1 92 –46.2 3 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.5.10 Analog Outputs Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, Figure 1-1. 5.5.10.1 Headphone Drivers The TLV320AIC3110 features a stereo headphone driver (HPL and HPR) that can deliver up to 30 mW per channel, at 3.3 V supply voltage, into a 16-Ω load.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com The TLV320AIC3110 has a short-circuit protection feature for the speaker drivers that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker-driver output stage.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.6 www.ti.com CLOCK Generation and PLL The TLV320AIC3110 supports a wide range of options for generating clocks for the ADC and DAC sections as well as interface and other control blocks as shown in Figure 5-36. The clocks for ADC and DAC require a source reference clock. This clock can be provided on variety of device pins such as MCLK, BCLK, or GPIO1 pins.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 DAC _ MOD _ CLK = DAC _ fS = CODEC _ CLKIN NDAC ´ MDAC CODEC _ CLKIN NDAC ´ MDAC ´ DOSR ADC _ MOD _ CLK = ADC _ fS = CODEC _ CLKIN NADC ´ MADC CODEC _ CLKIN NADC ´ MADC ´ AOSR (8) Table 5-40.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com DAC_MOD_CLK ADC_MOD_CLK ADC_CLK DAC_CLK BDIV_CLKIN N = 1, 2, ..., 127, 128 ÷N BCLK Figure 5-37. BCLK Output Options In the mode when TLV320AIC3110 is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), it can be driven as a divided value of BDIV_CLKIN. The division value can be programmed in page 0 / register 30, bits D6–D0 from 1 to 128.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 5-41. Maximum TLV320AIC3110 Clock Frequencies DVDD ≥ 1.65 V Clock CODEC_CLKIN ≤ 110 MHz ADC_CLK (ADC processing clock) ≤ 49.152 MHz ADC_PRB_CLK ≤ 24.576 MHz ADC_MOD_CLK 6.758 MHz ADC_fS 0.192 MHz DAC_CLK (DAC processing clock) ≤ 49.152 MHz DAC_PRB_CLK ≤ 49.152MHz with DRC disabled ≤ 48 MHz with DRC enabled DAC_MOD_CLK 6.758 MHz DAC_fS 0.192 MHz 5.6.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN: PLL _ CLKIN 10 MHz £ £ 20 MHz P • (11) 80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz R=1 The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a general-purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is available typically after 10 ms.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Powered on if internal oscillator is selected Internal Oscillator ÷8 0 Interval timers MCLK Programmable Divider Used for de-bounce time for headset detection logic, various power up timers and for generation of interrupts 1 P3/R16, Bits D6-D0 P3/R16, Bit D7 Figure 5-39. Interval Timer Clock Selection 5.7 5.7.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com The TLV320AIC3110 further includes programmability (page 0 / register 27, D0) to place the DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data LD(n+1) RD(n) = n'th sample of right channel data Figure 5-42.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N 1 5 4 3 2 1 0 N 1 5 4 LD(n) 3 2 1 N 1 0 RD(n) LD(n) = n'th sample of left channel data 5 LD (n+1) RD(n) = n'th sample of right channel data Figure 5-45.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 0 LSB 1 2 MSB n–1 n–2 n–3 0 LSB 1 2 MSB n–1 n–2 n–3 0 LSB 0 LSB n–1 n–2 n–3 1 2 n–1 n–2 n–3 MSB DOUT BCLK WCLK 1 Clock Before MSB 1/fS MSB 2 1 ADC Mono Channel (D0) ADC Mono Channel (D0) ADC Mono Channel (D1) 1/fS ADC Mono Channel (D1) n–1 T0202-03 www.ti.com Figure 5-47.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 5.7.1.4 www.ti.com DSP Mode The audio interface of the TLV320AIC3110 can be put into DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
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TLV320AIC3110 www.ti.com 5.7.2 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Primary and Secondary Digital Audio Interface Selection The audio serial interface on the TLV320AIC3110 has extensive I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections. Table 5-43 shows the primary and secondary audio interface selection and registers.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-44.
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TLV320AIC3110 www.ti.com 5.7.3.1 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 I2C Control Mode The TLV320AIC3110 supports the I2C control protocol, and responds to the I2C address of 0011 000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) RA(0) 8-bit Register Address (M) D(7) Slave Ack (S) D(0) 8-bit Register Data (M) Slave Ack (S) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-52.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 6 REGISTER MAP 6.1 TLV320AIC3110 Register Map All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are available for reading only. The TLV320AIC3110 contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 3 (0x03): OT FLAG D7–D2 D1 READ/ WRITE R R RESET VALUE XXXX XX 1 D0 R/W X BIT DESCRIPTION Reserved. Do not write to these bits. 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up 1: Normal operation Reserved. Do not write to these bits.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 8 (0x08): PLL D-VAL LSB (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION PLL fractional multiplier D-Val LSB bits D[7:0] Note that page 0 / Register 8 must be written immediately after page 0 / Register 7.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 1000 0000 (1) DESCRIPTION DAC OSR (DOSR) Setting DAC OSR(MSB) & DAC OSR(LSB) 00 0000 0000: DOSR=1024 00 0000 0001: DOSR=1 00 0000 0010: DOSR=2 ...
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 29 (0x1D): Codec Interface Control 2 D7–D6 D5 READ/ WRITE R/W R/W RESET VALUE 00 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1–D0 R/W 00 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D2 R/W 000 D1–D0 R/W 00 BIT DESCRIPTION Reserved 0: DIN-to-DOUT loopback is disabled. 1: DIN-to-DOUT loopback is enabled. 0: ADC-to-DAC loopback is disabled.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4 D3 R/W R/W 0 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION 000: ADC_WCLK is obtained from GPIO1 pin. 001: Reserved. 010: Reserved. 011: Reserved 100: Reserved. 101: Reserved. 110: Reserved. 111: Reserved. Reserved 0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 36 (0x24): ADC Flag Register D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 (1) R 0 D4–D0 R/W X XXXX BIT (1) DESCRIPTION 0: ADC PGA applied gain ≠ programmed gain 1: ADC PGA applied gain = programmed gain 0: ADC powered down 1: ADC powered up 0: AGC not saturated 1: AGC applied gain = maximum applicable gain by AGC Reserved. Write only zeros to these bits. Sticky flag bIts. These are read-only bits.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 39 (0x27): Overflow Flags D7 (1) READ/ WRITE R RESET VALUE 0 D6 (1) R 0 D5 (1) R 0 D4 D3 (1) R/W R 0 0 D2 D1 (1) R/W R 0 0 D0 R/W 0 BIT (1) DESCRIPTION Left-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. Right-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. DAC Barrel Shifter Output Overflow Flag 0: Overflow has not occurred.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 49 (0x31): INT2 Control Register D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 D1 R R/W 0 0 D0 R/W 0 READ/ WRITE R/W RESET VALUE 0000 0000 D7–D6 D5–D2 READ/ WRITE R/W R/W RESET VALUE XX 0000 D1 D0 R R/W X 0 READ/ WRITE R/W RESET VALUE XXXX XXXX BIT DESCRIPTION 0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 61 (0x3D): ADC Processing Blocks Selection READ/ WRITE R/W R/W RESET VALUE 000 0 0100 READ/ WRITE R RESET VALUE 0000 0000 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 01 D3–D2 R/W 01 D1–D0 R/W 00 D7–D4 D3 READ/ WRITE R/W R/W RESET VALUE 0000 1 D2 R/W 1 D1–D0 ( R/W 00 BIT D7–D5 D4–D0 DESCRIPTION Reserved. Write only default values. 0 0000: Reserved. Write only reset value.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 65 (0x41): DAC Left Volume Control BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0111 1111–0011 0001: Do not use. 0011 0000: Left-channel DAC digital 0010 1111: Left-channel DAC digital ... 0000 0001: Left-channel DAC digital 0000 0000: Left-channel DAC digital 1111 1111: Left-channel DAC digital ... 1000 0010: Left-channel DAC digital 1000 0001: Left-channel DAC digital 1000 0000: Reserved. Do not use.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 68 (0x44): DRC Control 1 D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 R/W 0 D4–D2 R/W 011 D1–D0 R/W 11 READ/ WRITE R R/W RESET VALUE 0 0111 BIT DESCRIPTION Reserved. Write only the reset value to these bits.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 71 (0x47): Left Beep Generator D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D0 R/W R/W 0 00 0000 BIT (1) (1) DESCRIPTION 0: Beep generator is disabled. 1: Beep generator is enabled (self-clearing based on beep duration). Reserved. Write only reset value.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 79 (0x4F): Beep Cos(x) LSB READ/ WRITE R/W RESET VALUE 1110 0011 READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D4 R/W R/W 0 00 D3 R/W 0 D2 D1–D0 R/W R/W 0 00 D7 READ/ WRITE R/W RESET VALUE 1 D6–D4 R/W 000 D3–D0 R/W 0000 BIT D7–D0 DESCRIPTION 8 LSBs out of 16 bits for cos(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 86 (0x56): AGC Control 1 D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D0 R/W 0000 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D1 R/W 00 000 D0 R/W 0 READ/ WRITE R/W R/W RESET VALUE 0 111 1111 D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 BIT DESCRIPTION 0: AGC disabled 1: AGC enabled 000: AGC target level = –5.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 0 / Register 90 (0x5A): AGC Decay Time D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 BIT DESCRIPTION 0000 0: AGC decay time = 1 × (512/fS) 0000 1: AGC decay time = 3 × (512/fS) 0001 0: AGC decay time = 5 × (512/fS) 0001 1: AGC decay time = 7 × (512/fS) 0010 0: AGC decay time = 9 × (512/fS) ...
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 93 (0x5D): AGC Gain-Applied Reading BIT D7–D0 READ/ WRITE R RESET VALUE XXXX XXXX DESCRIPTION 1110 1000: 1110 1001: ... 0000 0000: ... 0111 0011: 0111 0100: 0111 0101: 0111 0110: 0111 0111: Gain applied by AGC = –12 dB Gain applied by AGC = –11.5 dB Gain applied by AGC = 0 dB Gain Gain Gain Gain Gain applied by applied by applied by applied by applied by AGC AGC AGC AGC AGC = 57.5 dB = 58 dB = 58.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Registers 118 to 127: Reserved BIT D7–D0 6.3 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Do not write to these registers. Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls and MISC Logic Related Programmabilities Page 1 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 1 / Register 32 (0x20): Class-D Speaker Amplifier D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D1 D0 R/W R 00 011 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 0111 D2–D1 R/W 11 D0 R/W 0 D7 D6–D4 READ/ WRITE R/W R/W RESET VALUE 0 000 D3–D0 R/W 0000 BIT DESCRIPTION 0: Left-channel class-D output driver is powered down. 1: Left-channel class-D output driver is powered up.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing D7–D6 READ/ WRITE R/W RESET VALUE 00 D5 R/W 0 BIT D4 0 D3–D2 R/W 00 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 DESCRIPTION 00: DAC_L is not routed anywhere.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 1 / Register 40 (0x28): HPL Driver D7 D6–D3 READ/ WRITE R/W R/W RESET VALUE 0 0000 D2 R/W 0 D1 R/W 1 D0 R 0 BIT (1) DESCRIPTION Reserved. Write only zero to this bit. 0000: HPL driver PGA = 0 dB 0001: HPL driver PGA = 1 dB 0010: HPL driver PGA = 2 dB ... 1000: HPL driver PGA = 8 dB 1001: HPL driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits. 0: HPL driver is muted.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 1 / Register 43 (0x2B): SPR Driver D7–D5 D4–D3 READ/ WRITE R/W R/W RESET VALUE 000 00 D2 R/W 0 D1 D0 R/W R 0 0 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D3 R/W 00 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION Reserved. Write only zeros to these bits.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 1 / Register 47 (0x2F): MIC PGA D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0000 BIT DESCRIPTION 0: MIC PGA is controlled by bits D6–D0. 1: MIC PGA is at 0 dB. 000 0000: PGA = 0 dB 000 0001: PGA = 0.5 dB 000 0010: PGA = 1 dB ... 111 0110: PGA = 59 dB 111 0111: PGA = 59.5 dB 111 1000–111 1111: Reserved. Do not write these sequences to these bits.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Page 1 / Registers 51–127: Reserved BIT D7–D0 6.4 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Write only the reset value to these bits. Control Registers, Page 3: MCLK Divider for Programmable Delay Timer Default values shown for this page only become valid 100 μs following a hardware or software reset. Table 6-3.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 6-5.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-5.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Page 8 / Register 1 (0x01) : DAC Coefficient Buffer Control D7–D4 D3 D2 READ/ WRITE R/W R R/W RESET VALUE 0000 0 0 D1 R 0 D0 R/W 0 BIT DESCRIPTION Reserved. Write only the reset value.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-6.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 6-6.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-6.
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TLV320AIC3110 www.ti.com 6.7 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Control Registers, Page 9: DAC Digital Filter Coefficients Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 9 / Register 0 (0x00): Page Control Register READ/ WRITE R/W BIT D7–D0 RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 6.8 www.ti.com Control Registers, Page 12: DAC Programmable Coefficients Buffer B (1:63) Table 6-8. Page 12 DAC Buffer B Registers 116 REGISTER NUMBER RESET VALUE 1 0000 0000 Reserved. Do not write to this register.
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TLV320AIC3110 www.ti.com SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Table 6-8.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-8.
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TLV320AIC3110 www.ti.com 6.9 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127) Table 6-9. Page 13 DAC Buffer B Registers REGISTER NUMBER RESET VALUE 1 0000 0000 Reserved. Do not write to this register.
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TLV320AIC3110 SLAS647B – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April 2012) to Revision B • • • • • 120 Page Updated footnote in D7=1 table; added D6–D0 to the Register Value columns, and changed Analog Attenuation to Analog Gain. .....................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3110IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3110IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3110IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3110IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3110IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC3110IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.