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FEATURES

DESCRIPTION

TLV320AIC31

www.ti.com

............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008

LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

• Stereo Audio DAC:

– 100-dB (A-Weighted) Signal-to-Noise Ratio

The TLV320AIC31 is a low-power stereo audio codec

with a stereo headphone amplifier, as well as multiple

– 16-/20-/24-/32-Bit Data

inputs and outputs, programmable in single-ended or

– Supports Rates From 8 kHz to 96 kHz

fully-differential configurations. Extensive

– 3D/Bass/Treble/EQ/De-Emphasis Effects

stereo 48-kHz digital-to-analog converter (DAC)

• Stereo Audio ADC:

playback as low as 14 mW from a 3.3-V analog

– 92-dB (A-Weighted) Signal-to-Noise Ratio

supply, making it ideal for portable, battery-powered

– Supports Rates From 8 kHz to 96 kHz

audio and telephony applications.

• Six Audio Input Pins:

The record path of the TLV320AIC31 contains

– Two Stereo Differential/Single-Ended Inputs

integrated microphone bias, a digitally-controlled

stereo microphone pre-amp, and automatic gain

• Six Audio Output Drivers:

control (AGC), with mix/mux capability among the

– Stereo 8- Ω , 500-mW/Channel Speaker Drive

multiple analog inputs. The playback path includes

Capability

mix/mux capability from the stereo DAC and selected

– Stereo Fully-Differential or Single-Ended

inputs, through programmable volume controls to the

various outputs.

Headphone Drivers

– Fully Differential Stereo Line Outputs

The TLV320AIC31 contains four high-power output

drivers as well as two fully differential output drivers.

• Low Power: 14-mW Stereo, 48-kHz Playback

The high-power output drivers are capable of driving

With 3.3-V Analog Supply

a variety of load configurations, including up to four

• Programmable Input/Output Analog Gains

channels of single-ended, 16- Ω headphones using

• Automatic Gain Control (AGC) for Recording

ac-coupling capacitors, or stereo 16- Ω headphones in

a capless output configuration. In addition, pairs of

• Programmable Microphone Bias Level

drivers can be used to drive 8- Ω speakers in a BTL

• Programmable PLL for Flexible Clock

configuration at 500 mW per channel.

Generation

The stereo audio DAC supports sampling rates from

• I

C™ Control Bus

8 kHz to 96 kHz and includes programmable digital

• Audio Serial Data Bus Supports I

S™,

filtering in the DAC path for 3D, bass/treble/midrange

Left-/Right-Justified, DSP, and TDM Modes

effects, speaker equalization, and de-emphasis for

• Extensive Modular Power Control

32-kHz, 44.1-kHz, and 48-kHz rates. The

stereo-audio analog-to-digital converter (ADC)

• Power Supplies:

supports sampling rates from 8 kHz to 96 kHz and is

– Analog: 2.7 V to 3.6 V

preceded by programmable gain amplifiers providing

– Digital Core: 1.65 V to 1.95 V

up to +59.5 dB analog gain for low-level microphone

inputs.

– Digital I/O: 1.1 V to 3.6 V

• Available Packages: 5-mm × 5-mm,

The serial control bus supports the I

C protocol, while

the serial-audio data bus is programmable for I

32-Pin QFN

left-/right-justified, DSP, or TDM modes. A highly

programmable PLL is included for flexible clock

generation and support for all standard audio rates

from a wide range of available MCLKs, varying from

512 kHz to 50 MHz, with special attention paid to the

most popular cases of 12-MHz, 13-MHz, 16-MHz,

19.2-MHz, and 19.68-MHz system clocks.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 I2C, I2S are trademarks of NXP Semiconductors.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (84 pages)

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TLV320AIC31 www.ti.com .............................................................................................................................................
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com DESCRIPTION, CONTINUED The TLV320AIC31 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.65 V to 1.95 V, and a digital I/O supply of 1.1 V to 3.6 V. The device is available in a 5 × 5 mm, 32-lead QFN package. blank This integrated circuit can be damaged by ESD.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 DEVICE INFORMATION PIN ASSIGNMENTS 1 8 32 9 TLV320AIC31 25 16 24 17 TERMINAL FUNCTIONS TERMINAL NAME PIN NO.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). TJ Max TLV320AIC31 UNIT AVDD to AVSS1/2, DRVDD1/2 to DRVSS –0.3 to 3.9 V AVDDA1 to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD1/2 –0.1 to 0.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS At +25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, FS = 48 kHz, 16-bit audio data (unless otherwise noted).
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, FS = 48 kHz, 16-bit audio data (unless otherwise noted).
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, FS = 48 kHz, 16-bit audio data (unless otherwise noted). TLV320AIC31 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STEREO HEADPHONE DRIVER, continued –77 1-kHz output, PO = 10 mW, RL = 32 Ω 0.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS -20 -30 THD - Total Harmonic Distortion - dB Total Harmonic Distortion - dB -20 Capless, VDD = 3.6 V -40 AC-Coupled, VDD = 2.7 V -50 AC-Coupled, VDD = 3.6 V -60 -70 Capless, VDD = 2.7 V -80 -90 0.015 0.02 0.025 0.03 0.035 -30 -40 -50 -60 -70 -80 0.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) 0 -20 -40 dB -60 -80 -100 -120 -140 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency - kHz Figure 8. Line Input to ADC FFT Plot -10.00 -20.00 -30.00 VDD = 2.7 V VDD = 3.3 V VDD = 3.6 V THD -40.00 -50.00 -60.00 -70.00 -80.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) 38 36 SNR - dB 34 32 30 28 26 20 10 0 30 40 50 60 PGA Gain Setting - dB Figure 10. ADC SNR vs PGA Gain Setting, –65 dBFS Input 1.20 1.10 Gain Error - dB 1.00 0.90 0.80 0.70 0.60 Left ADC Right ADC 0.50 0.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Micbias - V TYPICAL CHARACTERISTICS (continued) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 MICBIAS = AVDD MICBIAS = 2.5 V MICBIAS = 2.0 V 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 AVDD - V Figure 12. MICBIAS Output Voltage vs AVDD 3.2 MICBIAS = AVDD 3.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL CIRCUIT CONFIGURATION IOVDD DSP or Media Processor 1 kW RESET MICBIAS SCL SDA RP AVDD_DAC DRVDD DRVDD 0.1 mF IN1LP IN1LR 1 kW 0.1 mF 1 mF 0.1 mF 1 mF 10 mF 0.1 mF 0.1 mF 1 mF A 0.47 mF FM Tuner/ Line In/ Mic AVDD 2.7 V to 3.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 OVERVIEW The TLV320AIC31 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com SDA tHD-STA ³ 2.0 ms SCL tSU-STA ³ 2.0 ms tSU-STO ³ 2.0 ms tHD-STA ³ 2.0 ms S Sr P S T0114-02 2 Figure 15. I C Interface Timing Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 The TLV320AIC31 also responds to and acknowledges a General Call, which consists of the master issuing a command with a slave address byte of 00h.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA are treated as data for the next incremental register.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 RIGHT-JUSTIFIED MODE In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com DSP MODE In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 DSP Mode word clock bit clock data in/out N-1 N-2 1 Left Channel Data offset 0 N-1 N-2 1 0 Right Channel Data Left Justified Mode word clock bit clock data in/out N-1 offset N-2 1 Left Channel Data 0 N-1 offset N-2 1 0 Right Channel Data Figure 22.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com AUDIO CLOCK GENERATION The audio converters in the TLV320AIC31 need an internal audio master clock at a frequency of 256 × FSref, which can be obtained in a variety of manners from an external clock signal applied to the device.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 When the PLL is enabled, FSref = (PLLCLK_IN × K × R) / (2048 × P), where P = 1, 2, 3,…, 8 R = 1, 2, …, 16 K = J.D J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by register 102, bits D5-D4 P, R, J, and D are register programmable.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Table 1 lists several example cases of typical MCLK rates and how to program the PLL to achieve FSref = 44.1 kHz or 48 kHz. Table 1. TYPICAL MCLK RATES FSref = 44.1 kHz MCLK (MHz) P R J D ACHIEVED FSref % ERROR 2.8224 1 1 32 0 44100.00 0.0000 5.6448 1 1 16 0 44100.00 0.0000 12.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 condition, and upon power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Input Signal Output Signal AGC Gain Decay Time Attack Time Figure 24. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 DIGITAL AUDIO PROCESSING The DAC channel consists of optional filters for de-emphasis and bass/treble/midrange level adjustment, speaker equalization, and 3D effects processing.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 DIGITAL INTERPOLATION FILTER The digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data are provided to the digital delta-sigma modulator and analog reconstruction filter stages.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com ANALOG OUTPUT COMMON-MODE ADJUSTMENT The output common-mode voltage and output range of the analog output are determined by an internal bandgap reference, in contrast to other codecs that may use a divided version of the supply.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 GAIN = 0, −1.5, −3, . . . −12 dB, Mute LINE1 LP LINE1 LM To Left ADC PGA GAIN = 0, −1.5, −3, . . . −12 dB, Mute LINE1 RP LINE1 RM Figure 27.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described above, the TLV320AIC31 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direction connection to the output drivers.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 DAC_L1 DAC_L2 DAC_L STEREO AUDIO DAC PGA_L PGA_R DAC_L1 DAC_R1 DAC_L3 DAC_R DAC_R1 DAC_R2 DAC_R3 VOLUME CONTROLS, MIXING LEFT_LOP LEFT_LOM Gain = 0dB to +9dB, Mute DAC_L3 PGA_L PGA_R DAC_L1 DAC_R1 VOLUME CONTROLS, MIXING DAC_R3 RIGHT_LOP RIGHT_LOM Gain = 0dB to +9dB, Mute Figure 29.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com The TLV320AIC31 includes an output level control on each output driver with limited gain adjustment from 0 dB to 9 dB. The output driver circuitry in this device are designed to provide a low distortion output while playing full-scale stereo DAC signals at a 0-dB gain setting.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com When these output drivers are powered down, they can be placed into a variety of output conditions based on register programming. If lowest power operation is desired, then the outputs can be placed into a 3-state condition, and all power to the output stage is removed.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 2: Codec Sample Rate Select Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7-D4 R/W 0000 ADC Sample Rate Select 0000: ADC FS = FSref/1 0001: ADC FS = FSref/1.5 0010: ADC FS = FSref/2 0011: ADC FS = FSref/2.5 0100: ADC FS = FSref/3 0101: ADC FS = FSref/3.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 12: Audio Codec Digital Filter Control Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D6 R/W 00 Left ADC High-pass Filter Control 00: Left ADC High-pass filter disabled 01: Left ADC High-pass filter –3-dB frequency = 0.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 15: BIT READ/ WRITE RESET VALUE D6-D0 R/W 0000000 Left ADC PGA Gain Control Register (continued) DESCRIPTION Left ADC PGA Gain Setting 0000000: Gain = 0.0-dB 0000001: Gain = 0.5-dB 0000010: Gain = 1.0-dB … 1110110: Gain = 59.0-dB 1110111: Gain = 59.5-dB 1111000: Gain = 59.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 20: BIT READ/ WRITE D7-D0 R/W RESET VALUE DESCRIPTION 0111100 Reserved. Do not write to this register.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 23: BIT READ/ WRITE D7-D0 R/W RESET VALUE Reserved Register DESCRIPTION 0111100 Reserved. Do not write to this register.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 34: (1) BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D3 R/W 00000 Left AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled. 00000: Debounce = 0-msec 00001: Debounce = 0.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 38: BIT READ/ WRITE High-Power Output Driver Control Register RESET VALUE DESCRIPTION D7-D6 R 00 Reserved. Write only 0s to these register bits.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 43: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W Left DAC Digital Volume Control Register DESCRIPTION Left DAC Digital Mute 0: The left DAC channel is not muted 1: The left DAC channel is muted 0000000 Left DAC Digital Volume Control Setting 0000000: Gain = 0.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Output Stage Volume Controls A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 66: BIT READ/ WRITE RESET VALUE D7-D0 R/W 0000000 DESCRIPTION Reserved. Write only '0000000' to this register.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 83: BIT READ/ WRITE RESET VALUE D7-D0 R/W 0000000 DESCRIPTION Reserved. Write only '0000000' to this register.
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TLV320AIC31 www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 Page 0 / Register 93: RIGHT_LOP/M Output Level Control Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7-D4 R/W 0000 D3 R/W 0 RIGHT_LOP/M Mute 0: RIGHT_LOP/M is muted 1: RIGHT_LOP/M is not muted D2 R/W 0 Reserved. Write only '0' to this register bit.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 1 / Register 0: BIT READ/ WRITE RESET VALUE D7-D1 X 0000000 D0 R/W 0 Page Select Register DESCRIPTION Reserved; write only 0s to these register bits. Page Select Bit Writing '0' to this bit sets Page-0 as the active page for following register accesses.
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TLV320AIC31 SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2006) to Revision B ..........................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC31IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC31IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC31IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TLV320AIC31IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.