TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Ultra Low Power Stereo Audio Codec Check for Samples: TLV320AIC3204 FEATURES • • 1 • • • • • • • 2 • • • • • • • Stereo Audio DAC with 100dB SNR 4.1mW Stereo 48ksps DAC Playback Stereo Audio ADC with 93dB SNR 6.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Package and Signal Descriptions Packaging and Ordering Information For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Table 1.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Table 1.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Electrical Characteristics Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT AVDD to AVSS –0.3 to 2.2 V DVDD to DVSS –0.3 to 2.2 V IOVDD to IOVSS –0.3 to 3.9 V LDOIN to AVSS –0.3 to 3.9 V Digital Input voltage to ground –0.3 to IOVDD + 0.3 V Analog input voltage to ground –0.3 to AVDD + 0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 THERMAL INFORMATION THERMAL METRIC (1) TLV320AIC3204 RHB (32 PINS) θJA Junction-to-ambient thermal resistance 31.4 θJCtop Junction-to-case (top) thermal resistance 21.4 θJB Junction-to-board thermal resistance 5.4 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 5.4 θJCbot Junction-to-case (bottom) thermal resistance 0.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Electrical Characteristics, ADC At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted. PARAMETER AUDIO ADC Input signal level (0dB) Single-ended, CM = 0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Electrical Characteristics, ADC (continued) At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC ICN Input signal level (0dB) Differential Input, CM = 0.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Electrical Characteristics, Bypass Outputs At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE Device Setup Load = 16Ω (single-ended), 50pF; Input and Output CM = 0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Electrical Characteristics, Microphone Interface At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MICROPHONE BIAS Bias voltage Bias voltage CM = 0.9V, LDOIN = 3.3V Micbias Mode 0, Connect to AVDD or LDOIN 1.25 V Micbias Mode 1, Connect to LDOIN 1.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Electrical Characteristics, Audio DAC Outputs At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Electrical Characteristics, Audio DAC Outputs (continued) At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Electrical Characteristics, LDO over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW DROPOUT REGULATOR (AVdd) Output Voltage LDOMode = 1, LDOIN > 1.95V 1.67 LDOMode = 0, LDOIN > 2.0V 1.72 LDOMode = 2, LDOIN > 2.05V 1.77 Output Voltage Accuracy V ±2 % 15 mV 5 mV 60 μA LDOMode = 1, LDOIN > 1.95V 1.67 V LDOMode = 0, LDOIN > 2.0V 1.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Electrical Characteristics, Misc. At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10μF on REF pin, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE Reference Voltage Settings Reference Noise CMMode = 0 (0.9V) 0.9 CMMode = 1 (0.75V) 0.75 CM = 0.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Electrical Characteristics, Logic Levels At 25°C, AVDD, DVDD, IOVDD = 1.8V PARAMETER TEST CONDITIONS MIN LOGIC FAMILY VIH Logic Level VIL TYP UNIT CMOS IIH = 5 μA, IOVDD > 1.6V 0.7 × IOVDD V IIH = 5μA, 1.2V ≤ IOVDD < 1.6V 0.9 × IOVDD V IIH = 5μA, IOVDD < 1.2V IOVDD V IIL = 5 μA, IOVDD > 1.6V –0.3 IIL = 5μA, 1.2V ≤ IOVDD < 1.6V IIL = 5μA, IOVDD < 1.2V VOH IOH = 2 TTL loads VOL IOL = 2 TTL loads 0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Interface Timing Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S) All specifications at 25°C, DVdd = 1.8V WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) DOUT th(DI) tS(DI) DIN Figure 3. I2S LJF and RJF Timing in Master Mode Table 2. I2S LJF and RJF Timing in Master Mode (see Figure 3) PARAMETER IOVDD=1.8V MIN IOVDD=3.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com WCLK th(WS) tL(BCLK) BCLK tH(BCLK) ts(WS) td(DO-WS) td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 4. I2S LJF and RJF Timing in Slave Mode Table 3. I2S LJF and RJF Timing in Slave Mode (see Figure 4) PARAMETER IOVDD=1.8V MIN IOVDD=3.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Typical DSP Timing Characteristics All specifications at 25°C, DVdd = 1.8V WCLK td(WS) td(WS) BCLK td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 5. DSP Timing in Master Mode Table 4. DSP Timing in Master Mode (see Figure 5) PARAMETER IOVDD=1.8V MIN IOVDD=3.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com I2C Interface Timing Figure 7. I2C Interface Timing Table 6. I2C Interface Timing PARAMETER TEST CONDITION Standard-Mode MIN TYP UNITS MAX SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4.0 0.8 μs tLOW LOW period of the SCL clock 4.7 1.3 μs tHIGH HIGH period of the SCL clock 4.0 0.6 μs tSU;STA Setup time for a repeated START condition 4.7 0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 SPI Interface Timing SS S t t Lead t t Lag td sck SCLK t sckl tf tr t sckh t v(DOUT) t dis MISO MSB OUT BIT 6 . . . 1 LSB OUT ta MOSI t hi t su MSB IN BIT 6 . . . 1 LSB IN Figure 8. SPI Interface Timing Diagram Timing Requirements At 25°C, DVdd = 1.8V Table 7. SPI Interface Timing (See Figure 8) PARAMETER TEST CONDITION IOVDD=1.8V MIN tsck SCLK Period (1) tsckh IOVDD=3.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Typical Characteristics Device Power Consumption Device power consumption largely depends on PowerTune configuration. For information on device power consumption, see the TLV320AIC3204 Application Reference Guide, literature number SLAA557. Typical Performance ADC SNR vs CHANNEL GAIN TOTAL HARMONIC DISTORTION vs HEADPHONE OUTPUT POWER 100 0 THD - Total Harmonic Distortion - dB SNR - Signal-to-Noise Ratio - dB CM=0.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 LDO DROPOUT VOLTAGE vs LOAD CURRENT LDO LOAD RESPONSE 350 20 DVDD LDO 15 Change In Output Voltage - mV 300 Dropout Voltage - mV 250 200 AVDD LDO 150 100 50 10 AVDD LDO 5 0 DVDD LDO -5 -10 -15 0 -20 0 10 20 30 Load - mA 40 50 0 10 Figure 13. 20 Load - mA 30 40 50 Figure 14. MICBIAS MODE 2, CM = 0.9V, LDOIN OP STAGE vs MICBIAS LOAD CURRENT 2.6 MicBIAS Voltage - mV 2.55 2.5 2.45 2.4 0 0.5 1 1.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com FFT SINGLE ENDED LINE INPUT TO ADC FFT at -1dBr vs FREQUENCY DAC PLAYBACK TO HEADPHONE FFT at -1dBFS vs FREQUENCY 0 0 DAC ADC -20 -20 -40 Power - dBr Power - dBFs -40 -60 -80 -60 -80 -100 -100 -120 -120 -140 0 5000 20000 15000 10000 f - Frequency - Hz 0 5000 10000 f - Frequency - Hz Figure 16. 15000 20000 Figure 17.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 TYPICAL CIRCUIT CONFIGURATION Host Processor Reset MCLK SCL SDA BCLK WCLK DIN DOUT SPI_Select 1k 1k 2.7k MICBIAS 1k 0.1uF 4700pF 0.1uF LOL 0.1uF 1k IN1_R TPA2012 0.1uF Class D Amp LOR 4700pF 0.1uF 0.1uF IN1_L 0.1uF 1.9...3.6V IN2_L LDOIN 0.1uF 1.0uF 10uF 0.1uF IN2_R 1.1...3.6V 1k 1k IOVDD MFP3/SCLK 0.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Table 8.
TLV320AIC3204 www.ti.com • • • • • • • SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Mute function Automatic gain control (AGC) Built in microphone bias Stereo digital microphone interface Channel-to-channel phase adjustment Fast charge of ac-coupling capacitors Anti thump Analog Low Power Bypass The TLV320AIC3204 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed from an analog input pin to an amplifier driving an analog output pin.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com ADC The TLV320AIC3204 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates from 8kHz to 192kHz. In order to provide optimal system power management, the stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Table 9.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com DAC The TLV320AIC3204 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Table 10. Overview – DAC Predefined Processing Blocks (1) Processing Block No. Interpolation Filter Channel 1st Order IIR Available Num.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0, Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word lengths, and to support the case when multiple TLV320AIC3204s may share the same audio bus.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 SPI Control In the SPI control mode, the TLV320AIC3204 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO, SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves).
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
TLV320AIC3204 SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
TLV320AIC3204 www.ti.com SLOS602B – SEPTEMBER 2008 – REVISED OCTOBER 2012 Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 44 0 0x2C 0x00 Page Select Register 44 1 0x2C 0x01 DAC Adaptive Filter Configuration Register 44 2-7 0x2C 0x02-0x07 Reserved 44 8-127 0x2C 0x08-0x7F DAC Coefficients Buffer-A C(0:29) 45-52 0 0x2D-0x34 0x00 Page Select Register 45-52 1-7 0x2D-0x34 0x01-0x07 Reserved.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3204IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3204IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3204IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3204IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3204IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3204IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC3204IRHBT VQFN RHB 32 250 210.0 185.0 35.
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