Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear-IC

SPI_Select

IN1_R

IN2_R

IN3_R

IN3_L

IN2_L

IN1_L

Left

ADC

DRC

Left

DAC

AGC

∗

ADC

Signal

Proc.

DAC

Signal

Proc.

Right

ADC

DRC

Right

DAC

AGC

∗ ∗

ADC

Signal

Proc.

DAC

Signal

Proc.

Vol. Ctrl

Data

Interface

Gain Adj.

0…

+47.5 dB

0.5 dB steps

0…+47.5 dB

0.5 dB

steps

-6...+14dB

1dB steps

-6...+29dB

1dB steps

-6...+29dB

1dB steps

-6...+14dB

1dB steps

SPI / I2C

Control Block

Pin Muxing / Clock Routing

Sec.

S I/F

Primary

S Interface

Dig

Mic

Inter

rupt

PLL

Mic

Bias

Ref

MicBias

Ref

Supplies

DVdd

Vsys

IOVdd

Avss (G ND)

DVss (GND)

IOVss (GND)

SDA/MOSI

MISO

SCLK

MCLK

GPIO

DOUT

DIN

BCLK

WCLK

miniDSP miniDSP

HPL

LOL

HPR

LOR

Reset

-30...0 dB

Charge

Pump

GND_ Sense

MicDet

VNEG

Fly_N

DVSS_CP

Fly_P

DV DD_CP

DRVdd_HP

SCL/SS

GND

AVdd

TLV320AIC3256

www.ti.com

SLOS630B –DECEMBER 2010–REVISED JANUARY 2013

Ultra Low Power Stereo Audio Codec With Embedded miniDSP

Check for Samples: TLV320AIC3256

FEATURES

APPLICATIONS

• Stereo Audio DAC with 100dB SNR

• Portable Navigation Devices (PND)

• 5.0mW Stereo 48ksps DAC-to-Ground- • Portable Media Player (PMP)

Centered Headphone Playback

• Mobile Handsets

• Stereo Audio ADC with 93dB SNR

• Communication

• 5.2mW Stereo 48ksps ADC Record

• Portable Computing

• PowerTune™

• Acoustic Echo Cancellation (AEC)

• Extensive Signal Processing Options

• Active Noise Cancellation (ANC)

• Embedded miniDSP

• Advanced DSP algorithms

• Six Single-Ended or 3 Fully-Differential Analog

Inputs DESCRIPTION

The TLV320AIC3256 (also called the AIC3256) is a

• Stereo Analog and Digital Microphone Inputs

flexible, low-power, low-voltage stereo audio codec

• Ground-Centered Stereo Headphone Outputs

with programmable inputs and outputs, PowerTune

• Very Low-Noise PGA

capabilities, fully-programmable miniDSP, fixed

predefined and parameterizable signal processing

• Low Power Analog Bypass Mode

blocks, integrated PLL, and flexible digital interfaces.

• Programmable Microphone Bias

• Programmable PLL

• 5mm x 5mm 40-pin QFN Package or 3.5mm x

3.3mm 42-ball WCSP

Figure 1. Simplified Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerTune is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

PAGE 1
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Ultra Low Power Stereo Audio Codec With Embedded miniDSP Check for Samples: TLV320AIC3256 FEATURES APPLICATIONS • • • • • • • • • • 1 2 • • • • • • • • • • • • • Stereo Audio DAC with 100dB SNR 5.0mW Stereo 48ksps DAC-to-GroundCentered Headphone Playback Stereo Audio ADC with 93dB SNR 5.
PAGE 2
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TLV320AIC3256 www.ti.
PAGE 4
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Table 1. TERMINAL FUNCTIONS (continued) 5x5mm 40PIN QFN (RSB) PIN NO. WCSP (YZF) NAME BALL NO.
PAGE 5
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Table 1. TERMINAL FUNCTIONS (continued) 5x5mm 40PIN QFN (RSB) PIN NO. WCSP (YZF) NAME BALL NO.
PAGE 6
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Table 1. TERMINAL FUNCTIONS (continued) 5x5mm 40PIN QFN (RSB) PIN NO. 40 6 WCSP (YZF) NAME BALL NO. B1 DVdd TYPE PWR DESCRIPTION Digital voltage supply 1.26V – 1.
PAGE 7
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Electrical Characteristics Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT AVdd to AVss –0.3 to 2.2 V DVdd to DVss –0.3 to 2.2 V Vsys to DVss –0.3 to 5.5 V IOVdd to IOVss –0.3 to 3.9 V Digital Input voltage IOVss to IOVdd + 0.3 V Analog input voltage AVss to AVdd + 0.
PAGE 8
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com THERMAL INFORMATION THERMAL METRIC Junction-to-ambient thermal resistance (2) θJA (3) RSB (QFN) (1) YZF (DSGBA) (1) 48 PINS 42 PINS 32.3 49.7 θJCtop Junction-to-case (top) thermal resistance 22.5 0.1 θJB Junction-to-board thermal resistance (4) 6.1 7.7 ψJT Junction-to-top characterization parameter (5) 0.3 0.1 ψJB Junction-to-board characterization parameter (6) 6 7.7 1.
PAGE 9
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Electrical Characteristics, ADC At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER AUDIO ADC (1) (2) TEST CONDITIONS MIN Input signal level (for 0dB output) Single-ended, CM = 0.9V MAX UNIT SNR Signal-to-noise ratio, Aweighted (1) (2) DR Dynamic range A-weighted (1) 0.
PAGE 10
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Electrical Characteristics, ADC (continued) At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC (Gain = 40dB) Input signal level (for 0dB output) Differential Input, CM = 0.9V, Channel Gain = 40dB 10 mVRMS Inputs ac-shorted to ground, input referred noise 2.8 μVRMS 0.
PAGE 11
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Electrical Characteristics, Bypass Outputs At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE Device Setup Load = 16Ω (single-ended), 50pF; Input and Output CM = 0.
PAGE 12
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Electrical Characteristics, Microphone Interface At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MICROPHONE BIAS Bias voltage Bias voltage CM = 0.9V, DRVdd_HP = 1.8V Micbias Mode 0, Connect to AVdd or DRVdd_HP 1.
PAGE 13
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Electrical Characteristics, Audio DAC Outputs At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 VRMS 87 100 dB –60dB 1kHz input full-scale signal, Word length = 20 bits 100 dB –81 AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT (CM=0.
PAGE 14
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Electrical Characteristics, Audio DAC Outputs (continued) At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Gain Error 500mVRMS output, 1kHz input full scale signal 0.
PAGE 15
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Electrical Characteristics, Misc. At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fS (Audio) = 48kHz, CREF = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE Reference Voltage Settings Reference Noise CMMode = 0 (0.9V) 0.9 CMMode = 1 (0.75V) 0.75 CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, CREF = 1μF V μVRMS 1.
PAGE 16
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Interface Timing Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S) All specifications at 25°C, DVdd = 1.8V WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) DOUT th(DI) tS(DI) DIN Figure 4. I2S/LJF/RJF Timing in Master Mode Table 2. I2S/LJF/RJF Timing in Master Mode (see Figure 4) PARAMETER IOVDD=1.8V MIN IOVDD=3.
PAGE 17
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 WCLK th(WS) tL(BCLK) BCLK tH(BCLK) ts(WS) td(DO-WS) td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 5. I2S/LJF/RJF Timing in Slave Mode Table 3. I2S/LJF/RJF Timing in Slave Mode (see Figure 5) PARAMETER IOVDD=1.8V MIN IOVDD=3.
PAGE 18
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Typical DSP Timing Characteristics All specifications at 25°C, DVdd = 1.8V WCLK td(WS) td(WS) BCLK td(DO-BCLK) DOUT th(DI) ts(DI) DIN Figure 6. DSP Timing in Master Mode Table 4. DSP Timing in Master Mode (see Figure 6) PARAMETER IOVDD=1.8V MIN IOVDD=3.
PAGE 19
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 I2C Interface Timing Figure 8. I2C Interface Timing Table 6. I2C Interface Timing PARAMETER TEST CONDITION Standard-Mode MIN TYP 0 Fast-Mode MAX 0 TYP UNITS MAX fSCL SCL clock frequency tH(STA) Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4.0 0.8 μs tLOW LOW period of the SCL clock 4.7 1.3 μs tHIGH HIGH period of the SCL clock 4.0 0.
PAGE 20
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com SPI Interface Timing SS S t t Lead t t Lag td sck SCLK t sckl tf tr t sckh t v(DOUT) t dis MISO MSB OUT BIT 6 . . . 1 LSB OUT ta MOSI t hi t su MSB IN BIT 6 . . . 1 LSB IN Figure 9. SPI Interface Timing Diagram Timing Requirements (See Figure 9) At 25°C, DVdd = 1.8V Table 7. SPI Interface Timing PARAMETER TEST CONDITION IOVDD=1.8V MIN tsck SCLK Period tsckh IOVDD=3.
PAGE 21
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Typical Characteristics Device Power Consumption Device power consumption largely depends on PowerTune configuration. For information on device power consumption, see the TLV320AIC3256 Application Reference Guide, literature number SLAU306.
PAGE 22
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com HEADPHONE SNR AND OUTPUT POWER vs OUTPUT COMMON MODE SETTING 105 60 50 SNR 95 90 40 85 30 80 Output Power 75 20 Power Delivered - mW SNR - Signal-to-Noise Ratio - dB 100 70 10 65 60 0 0 0.75 0.9 1.25 1.5 Output Common Mode Setting 1.65 Figure 14.
PAGE 23
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 DAC PLAYBACK TO HEADPHONE FFT @ -1dBFS (GROUND-CENTERED MODE) vs FREQUENCY DAC PLAYBACK TO LINE-OUT FFT @ -1dBFS vs FREQUENCY 0 0 DAC -20 -20 -40 -40 Power - dBr Power - dBr DAC -60 -80 -60 -80 -100 -100 -120 -120 -140 0 5000 10000 f - Frequency - Hz 15000 20000 -140 0 5000 Figure 17.
PAGE 24
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Typical Circuit Configuration Figure 21. Typical Circuit Configuration APPLICATION OVERVIEW The TLV320AIC3256 offers a wide range of configuration options. Figure 1 shows the basic functional blocks of the device.
PAGE 25
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Multifunction Pins Table 8 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO). Table 8.
PAGE 26
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Analog Audio I/O The analog IO path of the TLV320AIC3256 features a large set of options for signal conditioning as well as signal routing: • 6 analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration • 2 programmable gain amplifiers (PGA) with a range of 0 to +47.
PAGE 27
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Line Outputs The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the analog input common-mode setting, or 1.65V. With output common-mode setting of 1.65V and DRVdd_HP supply at 3.3V the line-level drivers can drive up to 1Vrms output signal.
PAGE 28
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Table 9.
PAGE 29
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 DAC The TLV320AIC3256 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter.
PAGE 30
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Table 10. Overview – DAC Predefined Processing Blocks (1) Processing Block No. Interpolation Filter Channel 1st Order IIR Available Num.
PAGE 31
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 The TLV320AIC3256 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.
PAGE 32
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com SPI Control In the SPI control mode, the TLV320AIC3256 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO, SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves).
PAGE 33
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
PAGE 34
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
PAGE 35
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
PAGE 36
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com Table 11. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 26-34 1-7 0x1A-0x22 0x01-0x07 Reserved.
PAGE 37
TLV320AIC3256 www.ti.com SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 REVISION HISTORY Changes from Revision initial (December 2010) to Revision A Page • Changed "mV" to "mVRMS" for Input signal level units ..................................................................................................... 10 • Changed Gain Error value from 0.7 to 0.8 .........................................................................................................................
PAGE 38
TLV320AIC3256 SLOS630B – DECEMBER 2010 – REVISED JANUARY 2013 www.ti.com REVISION HISTORY Changes from Revision A (December 2010) to Revision B Page • Added WCSP package (YZF) ............................................................................................................................................... 1 • Updated block diagram to include Vsys pin ..........................................................................................................................
PAGE 39
PACKAGE OPTION ADDENDUM www.ti.
PAGE 40
PACKAGE OPTION ADDENDUM www.ti.
PAGE 41
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3256IRSBT WQFN RSB 40 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3256IYZFR DSBGA YZF 42 2500 330.0 12.4 3.5 3.7 0.81 8.0 12.0 Q1 TLV320AIC3256IYZFT DSBGA YZF 42 250 330.0 12.4 3.5 3.7 0.81 8.0 12.
PAGE 42
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3256IRSBT WQFN RSB TLV320AIC3256IYZFR DSBGA YZF 40 250 210.0 185.0 35.0 42 2500 367.0 367.0 35.0 TLV320AIC3256IYZFT DSBGA YZF 42 250 367.0 367.0 35.
PAGE 43
PAGE 44
PAGE 45
PAGE 46
D: Max = 3.499 mm, Min =3.439 mm E: Max = 3.299 mm, Min =3.
PAGE 47
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.