TLV320AIC33 www.ti.com ...........................................................................................................................................
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com DESCRIPTION (CONTINUED) The TLV320AIC33 operates from an analog supply of 2.7 V–3.6 V, a digital core supply of 1.65 V–1.95 V, and a digital I/O supply of 1.1 V–3.6 V. The device is available in 5 × 5-mm, 80-ball MIcroStar Junior™ BGA and 7 × 7-mm, 48-lead QFN.
TLV320AIC33 www.ti.com ...........................................................................................................................................
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL 4 DESCRIPTION BGA BALL QFN J1 25 AVDD Analog DAC Voltage Supply, 2.7 V–3.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TJ Max (2) VALUE UNIT AVDD to AVSS, DRVDD to DRVSS –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD –0.1 to 0.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MICROPHONE BIAS 2.0 Bias voltage Programmable settings, load = 750 Ω 2.25 2.5 2.75 V AVDD0.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –77 1-kHz output, PO = 5 mW, RL = 32 Ω 0.014 –76 1-kHz output, PO = 10 mW, RL = 32 Ω 0.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS -20 -30 -30 Capless, VDD = 3.6 V -40 Total Harmonic Distortion Total Harmonic Distortion - dB -20 AC-Coupled, VDD = 2.7 V -50 AC-Coupled, VDD = 3.6 V -60 -70 Capless, VDD = 2.7 V -80 -90 0.015 0.02 0.025 0.03 0.035 0.04 Power - W AC-Coupled, VDD = 2.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) 0 -20 -40 dB -60 -80 -100 -120 -140 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency - kHz Figure 8. Line Input to ADC FFT Plot -10.00 -20.00 -30.00 VDD = 2.7 V VDD = 3.3 V VDD = 3.6 V THD -40.00 -50.00 -60.00 -70.00 -80.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) 38 36 SNR - dB 34 32 30 28 26 0 10 20 30 40 50 60 PGA Gain Setting - dB Figure 10. ADC SNR vs PGA Gain Setting, –65 dBFS Input 1.20 1.10 Gain Error - dB 1.00 0.90 0.80 0.70 0.60 Left ADC Right ADC 0.50 0.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Micbias - V TYPICAL CHARACTERISTICS (continued) 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 MICBIAS=AVDD MICBIAS=2.5V MICBIAS=2.0V 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 AVDD - V Figure 12. MICBIAS Output Voltage vs AVDD 3.2 MICBIAS=AVDD 3 Micbias - V 2.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD I2C ADDRESS Rp Multimedia DBB / Processor Modem MFP1 MFP2 MFP0 GPIO1 GPIO2 MFP3 DIN DOUT WCLK BCLK MCLK SCL SDA RESET Rp AVDD (2.7V−3.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com OVERVIEW The TLV320AIC33 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 /SS SCLK MOSI RA(6) RA(5) RA(0) DON’T CARE Read 7-Bit Register Address MISO D(7) D(6) D(0) 8-Bit Register Data Figure 16.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to register 0, the page control register, to change the active page back to page 0.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 SDA tHD-STA ³ 2.0 ms SCL tSU-STA ³ 2.0 ms tSU-STO ³ 2.0 ms tHD-STA ³ 2.0 ms S Sr P S T0114-02 2 Figure 17. I C Interface Timing I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it will receive a not−acknowledge because no device is present at that address to pull the line LOW.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 WCLK GPIO1 GPIO2 BCLK DIN DOUT MFP3 Audio Serial Data Bus Figure 20.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 n-1 n-2 n-3 n-1 n-2 n-3 Figure 23. Left Justified Serial Data Bus Mode Operation I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com 1/fs WCLK BCLK Right Channel Left Channel SDIN/SDOUT n–1 n–2 n–3 n–4 LSB MSB 2 1 0 n–1 n–2 n–3 LSB MSB 2 1 0 n–1 LSB T0152-01 Figure 25.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 DSP Mode word clock bit clock data in/out N-1 N-2 1 Left Channel Data offset 0 N-1 N-2 1 0 Right Channel Data Left Justified Mode word clock bit clock data in/out N-1 offset N-2 1 Left Channel Data 0 N-1 offset N-2 1 0 Right Channel Data Figure 26.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com MCLK GPIO2 BCLK PLL_CLKIN CLKDIV_CLKIN CLKDIV_IN PLL_IN Q = 3,3, . . . . ,16,17 K = J.D J = 1,2,3,. . . , 62,63 D= 0000,0001, . . . ,9998,9999 R= 1,2,3,4, . . . ,15,16 P= 1,2, . . . .
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 When the PLL is disabled, Fsref = CLKDIV_IN / (128 × Q) Where Q = 2, 3, …, 17 CLKDIV_IN can be MCLK, BCLK, or GPIO2, selected by register 102, bits D7-D6. NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve Fsref = 44.1 kHz or 48 kHz. Fsref = 44.1 kHz MCLK (MHz) P R J D ACHIEVED FSREF % ERROR 2.8224 1 1 32 0 44100.00 0.0000 5.6448 1 1 16 0 44100.00 0.0000 12.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 Fs to the final output sampling rate of Fs. The decimation filter provides a linear phase output response with a group delay of 17/Fs.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Input Signal Output Signal AGC Gain Decay Time Attack Time Figure 28. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 DIGITAL AUDIO PROCESSING The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 filter is designed to maintain at least 65-dB rejection of images that land below 7.455 Fs.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Table 3. Appropriate Settings (continued) CM SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD 1.65 V 3.3 V – 3.6 V 1.8 V – 1.95 V 1.8 V 3.6 V 1.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 Three fully-differential analog inputs can similarly be mixed into the right ADC PGA as well, consisting of LINE1RP-LINE1RM, LINE2RP-LINE2RM, and LINE1LP-LINE1LM.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described above, the TLV320AIC33 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direction connection to the output drivers.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC33 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 33 and Figure 34.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com LINE2L/MIC2L 0dB to -78dB LINE2R/MIC2R 0dB to -78dB PGA_L 0dB to -78dB + PGA_R 0dB to -78dB DAC_L1 0dB to -78dB DAC_R1 0dB to -78dB Figure 34.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 5. driving stereo headphones in single-ended configuration with two drivers, while the remaining two drivers are connected in BTL configuration to an 8-Ω speaker.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 AVDD Stereo g s MICBIAS MICDET s To Detection block MIC3(L/R) Cellular g m s HPLOUT Stereo + Cellular g m s s HPROUT m = mic HPRCOM s = speaker To detection block 1.35 HPLCOM g = ground/midbias Figure 36.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com This switch closes when MICDET jack is removed To Detection block HPLOUT HPLCOM HPRCOM HPROUT Figure 38. Configuration of device for jack detection using a fully differential stereo headphone output connection. GENERAL PURPOSE I/O AIC33 has two dedicated pins for General Purpose IO.
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TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Page 0 / Register 14: BIT READ/ WRITE RESET VALUE D3 (1) R/W 0 D2–D0 R 000 Headset / Button Press Detection Register B (continued) DESCRIPTION Stereo Output Driver Configuration B Note: do not set bits D6 and D3 both high at the same time.
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TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 Page 0 / Register 32: BIT READ/ WRITE RESET VALUE D7–D0 R 00000000 DESCRIPTION Left Channel Gain Applied by AGC Algorithm 11101000: Gain = –12.0-dB 11101001: Gain = –11.5-dB 11101010: Gain = –11.0-dB … 00000000: Gain = 0.0-dB 00000001: Gain = +0.5-dB … 01110110: Gain = +59.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Page 0 / Register 35: (1) Right AGC Noise Gate Debounce Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D3 R/W 00000 Right AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled. 00000: Debounce = 0-msec 00001: Debounce = 0.
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TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.
TLV320AIC33 www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 Page 0 / Register 43: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W Left DAC Digital Volume Control Register DESCRIPTION Left DAC Digital Mute 0: The left DAC channel is not muted 1: The left DAC channel is muted 0000000 Left DAC Digital Volume Control Setting 0000000: Gain = 0.
TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Table 4. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 15 -7.5 45 -22.6 75 -37.7 105 -52.7 16 -8.0 46 -23.1 76 -38.2 106 -53.7 17 -8.
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TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Page 0 / Register 86: LEFT_LOP/M Output Level Control Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7-D4 R/W 0000 D3 R/W 0 LEFT_LOP/M Mute 0: LEFT_LOP/M is muted 1: LEFT_LOP/M is not muted D2 R/W 0 Reserved. Write only zero to this register bit.
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TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Page 0 / Register 98: GPIO1 Control Register (continued) BIT READ/ WRITE RESET VALUE DESCRIPTION D2 R/W 0 GPIO1 Interrupt Duration Control 0: GPIO1 Interrupt occurs as a single active-high pulse of typical duration 2ms.
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TLV320AIC33 SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com Page 0 / Register 102: BIT READ/ WRITE RESET VALUE D5-D4 R/W 00 D3-D0 R/W 0010 Clock Generation Control Register (continued) DESCRIPTION PLLCLK_IN Source Selection 00: PLLCLK_IN uses MCLK 01: PLLCLK_IN uses GPIO2 10: PLLCLK _IN uses BCLK 11: Reserved. Do not use.
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PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com (4) 26-Aug-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC33IRGZR TLV320AIC33IRGZT TLV320AIC33IZQER Package Package Pins Type Drawing VQFN RGZ 48 VQFN RGZ ZQE BGA MI CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC33IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 TLV320AIC33IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 TLV320AIC33IZQER BGA MICROSTAR JUNIOR ZQE 80 2500 338.1 338.1 20.
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