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TLV320DAC3100

www.ti.com

SLAS671A –FEBRUARY 2010–REVISED MAY 2012

Low-Power Stereo Audio DAC With Audio Processing

and Mono Class-D Speaker Amplifier

Check for Samples: TLV320DAC3100

1 INTRODUCTION

1.1 Features 1.2 Applications

1234

• Stereo Audio DAC with 95-dB SNR

• Portable Audio Devices

• Supports 8-kHz to 192-kHz Sample Rates

• Mobile Internet Devices

• Mono Class-D BTL Speaker Driver (2.5 W Into

• eBooks

4-Ω or 1.6 W Into 8-Ω)

• Two Single-Ended Inputs With Mixing and

1.3 Description

Output Level Control

• Stereo Headphone/Lineout and Mono Class-D

The TLV320DAC3100 is a low-power, highly

Speaker Outputs Available

integrated, high-performance stereo audio DAC with

• Microphone Bias

24-bit stereo playback and digital audio processing

• Headphone Detection blocks.

• 25 Built-in Digital Audio Processing Blocks

The device integrates headphone drivers and

(PRB_P1 – PRB_P25) Providing Biquad and FIR

speaker drivers. The mono speaker driver can drive

Filters, DRC, and 3-D Structures

loads down to 4 Ω. The TLV320DAC3100 has a suite

• Digital Mixing Capability

of built-in processing blocks for digital audio

• Pin Control or Register Control for Digital-

processing. The digital audio data format is

Playback Volume-Control Settings

programmable to work with popular audio standard

• Digital Sine-Wave Generator for Beeps and Key

protocols (I

S, left/right-justified) in master, slave,

Clicks (PRB_P25)

DSP, and TDM modes. Bass boost, treble, or EQ can

• Programmable PLL for Flexible Clock

be supported by the programmable digital signal-

Generation

processing block. An on-chip PLL provides the high-

• I

S, Left-Justified, Right-Justified, DSP, and

speed clock needed by the digital signal-processing

TDM Audio Interfaces

block. The volume level can be controlled either by

• I

C™ Control With Register Auto-Increment

pin control or by register control. The audio functions

• Full Power-Down Control

are controlled using the I

C serial bus.

• Power Supplies:

The TLV320DAC3100 has a programmable digital

– Analog: 2.7 V–3.6 V

sine-wave generator and is available in a 32-pin QFN

– Digital Core: 1.65 V–1.95 V

package.

– Digital I/O: 1.1 V–3.6 V

TEXT ADDED FOR ALIGNMENT

– Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)

• 5-mm × 5-mm 32-QFN Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of NXP B.V.

3MATLAB is a trademark of The MathWorks, Inc.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (98 pages)

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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Low-Power Stereo Audio DAC With Audio Processing and Mono Class-D Speaker Amplifier Check for Samples: TLV320DAC3100 1 INTRODUCTION 1.1 Features • Stereo Audio DAC with 95-dB SNR • Supports 8-kHz to 192-kHz Sample Rates • Mono Class-D BTL Speaker Driver (2.5 W Into 4-Ω or 1.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320DAC3100 QFN-32 RHB –40°C to 85°C 2.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO.
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TLV320DAC3100 www.ti.com 3.2 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX AVDD (1) (2) 2.7 3.3 3.6 Referenced to DVSS(2) 1.65 1.8 1.95 Referenced to HPVSS(2) 2.7 3.3 3.6 Referenced to SPKVSS(2) 2.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.
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TLV320DAC3100 www.ti.com 3.4 3.4.1 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Timing Characteristics I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tr td(WS) BCLK tf tS(DI) th(DI) DIN T0145-10 PARAMETER td(WS) ts(DI) th(DI) tr tf WCLK delay DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 8 8 25 25 IOVDD = 3.3 V MIN MAX 20 6 6 10 10 UNIT ns ns ns ns ns Figure 3-1.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com I2S/LJF/RJF Timing in Slave Mode 3.4.2 All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tr th(WS) tS(WS) tH(BCLK) BCLK tL(BCLK) tS(DI) tf DIN th(DI) T0145-11 PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) ts(DI) th(DI) tr tf BCLK high period BCLK low period WCLK setup WCLK hold DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 35 35 8 8 8 8 4 4 IOVDD = 3.
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TLV320DAC3100 www.ti.com 3.4.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK td(WS) td(WS) tf BCLK tr tS(DI) DIN th(DI) T0146-09 PARAMETER td(WS) ts(DI) th(DI) tr tf WCLK delay DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 8 8 25 25 IOVDD = 3.3 V MIN MAX 20 8 8 10 10 UNIT ns ns ns ns ns Figure 3-3.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 3.4.4 www.ti.com DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tS(WS) tS(WS) th(WS) th(WS) tf tL(BCLK) BCLK tS(DI) tH(BCLK) tr DIN th(DI) T0146-10 PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) ts(DI) th(DI) tr tf BCLK high period BCLK low period WCLK setup WCLK hold DIN setup DIN hold Rise time Fall time IOVDD = 1.
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TLV320DAC3100 www.ti.com 3.4.5 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time, (repeated) START condition.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 4 TYPICAL PERFORMANCE 4.1 DAC Performance Added Text for Spacing AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −40 Amplitude − dBFS −40 Amplitude − dBFS AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.
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TLV320DAC3100 www.ti.com 4.2 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Class-D Speaker Driver Performance Added Text for Spacing TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 0 AVDD = HPVDD = 3.3 V IOVDD = 3.3 V SPKVDD = 5.5 V DVDD = 1.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 4.3 www.ti.com Analog Bypass Performance Added Text for Spacing AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −40 Amplitude − dBFS −40 Amplitude − dBFS AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 f − Frequency − kHz 10 G008 Figure 4-8.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5 APPLICATION INFORMATION 5.1 Typical Circuit Configuration +3.3VA SVDD 0.1 mF IOVDD 22 mF 0.1 mF 22 mF 0.1 mF 0.1 mF 10 mF 10 mF Rp ´ 2 SPKVDD SPKVDD HPVDD AVDD SPKVSS SPKVSS AVSS HPVSS SDA HOST PROCESSOR SCL GPIO1 MCLK SPKP SPKP SPKM SPKM WCLK DIN BCLK 8-W or 4-W Speaker TLV320DAC3100 RESET To External MIC Circuitry Analog In MICBIAS HPL AIN1 HPR Stereo Headphone Out AIN2 AVDD 34.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 • • • • • • • • www.ti.com Digital sine-wave generator for clicks and beeps Stereo headphone/lineout amplifier Class-D mono amplifier capable of driving 4-Ω speakers Pin-controlled or register-controlled volume level Power-down de-pop and power-up soft start Analog inputs I2C control interface Power-down control block Following a toggle of the RESET pin or a software reset, the device operates in the default mode.
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TLV320DAC3100 www.ti.com 5.2.1.5 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Software Power Down By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit block can be controlled by writing to the appropriate control register. This approach allows the lowest power-supply current for the functionality required. However, when a block is powered down, all of the register settings are maintained as long as power is still being applied to the device. 5.2.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.5 mW Table 5-2. PRB_P7 Alternative Processing Blocks, 24.5 mW 5.3.2 Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.17 PRB_P2 A 2.62 PRB_P3 A 2 PRB_P8 B 0.99 PRB_P9 B 0.5 PRB_P10 B 1.46 PRB_P11 B 0.66 PRB_P23 A 1.43 PRB_P24 A 2.69 PRB_P25 A 2.92 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.
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TLV320DAC3100 www.ti.com 5.3.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 22.44 mW Table 5-5. PRB_P7 Alternative Processing Blocks, 22.44 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 0.02 PRB_P2 A 0.31 PRB_P3 A 0.23 PRB_P8 B 0.28 PRB_P9 B –0.03 PRB_P10 B 0.14 PRB_P11 B 0.05 PRB_P23 A 0.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.42 mW Table 5-8. PRB_P12 Alternative Processing Blocks, 14.42 mW 5.3.5 Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.16 PRB_P5 A 0.3 PRB_P6 A 0.2 PRB_P13 B 0.15 PRB_P14 B 0.07 PRB_P15 B 0.18 PRB_P16 B 0.09 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the model of microphone that is selected, optimal performance might be obtained at another setting, so the performance at a given setting should be verified. The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current consumption occurs when MICBIAS is set at AVDD.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 • • www.ti.com 3D effect Digital sine-wave (beep) generator The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. Table 5-11. Overview – DAC Predefined Processing Blocks Processing Block No.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D BiQuad E Interp. Filter A,B BiQuad F HPF ´ to Modulator Digital Volume Ctrl DRC Figure 5-3. Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15 5.5.1.2.3 Six Biquads, First-Order IIR, Filter A or B BiQuad A IIR from Interface BiQuad B BiQuad C BiQuad D BiQuad E Interp.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C BiQuad A IIR BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to Modulator from Interface HPF Digital Volume Ctrl DRC Figure 5-8. Signal Chain for PRB_P18 and PRB_P21 5.5.1.2.8 Four Biquads, First-Order IIR, Filter C IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to modulator Digital Volume Ctrl Figure 5-9.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.2.10 Five Biquads, DRC, 3D, Filter A IIR from Left Left Channel Interface + BiQuad CL BiQuad BL + BiQuad DL BiQuad EL BiQuad FL Interp. Filter A to Modulator ´ + HPF + BiQuad AL + - Digital Volume Ctrl DRC 3D PGA BiQuad AR from Right Channel Interface IIR Right + BiQuad BR + BiQuad CR BiQuad DR BiQuad ER BiQuad FR HPF Interp. Filter A to Modulator ´ Digital Volume Ctrl DRC Figure 5-11.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.3 www.ti.com DAC User-Programmable Filters Depending on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.3.1 First-Order IIR Section The IIR is of first order and its transfer function is given by H(z) = N0 + N1z -1 215 - D1z -1 (1) The frequency response for the first-order IIR section with default coefficients is flat. Table 5-13.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-14. DAC Biquad Filter Coefficients (continued) Filter Coefficient Biquad D Biquad E Biquad F 5.5.1.4 Left DAC Channel Right DAC Channel Default (Reset) Value N0 Page 8 / register 32 and page 8 / register 33 Page 8 / register 96 and page 8 / register 97 0x7FFF (decimal 1.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DAC Channel Response for Interpolation Filter A (Red Line Corresponds to –65 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 1 2 5 6 3 4 Frequency Normalized to fS 7 Figure 5-14. Frequency Response of DAC Interpolation Filter A 5.5.1.4.2 Interpolation Filter B Filter B is specifically designed for an fS up to 96 ksps. Thus, the flat pass-band region easily covers the required audio band of 0 kHz–20 kHz. Table 5-16.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-17. Specification for DAC Interpolation Filter C Parameter Condition Value (Typical) Unit Filter-gain pass band 0 … 0.35 fS ±0.03 dB Filter-gain stop band 0.6 fS … 1.4 fS –43 dB 13/fS s Filter group delay DAC Channel Response for Interpolation Filter C (Red Line Corresponds to –43 dB) 0 Magnitude – dB –10 –20 –30 –40 –50 –60 –70 0 0.2 0.4 0.6 0.8 1 1.2 Frequency Normalized to fS 1.4 Figure 5-16.
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TLV320DAC3100 www.ti.com 5.5.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Volume-Control Pin The volume-control pin is not enabled by default, but it can be enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63, bits D1–D0.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com The VOL/MICDET pin connection and functionality are shown in Figure 5-17. 24 dB to Mute Digital DAC_L D-S DAC Vol Ctl Processing Blocks 24 dB to Mute AVDD Digital VREF IN R1 AVDD VOL/ MICDET DAC_R Vol Ctl D-S DAC Processing Blocks 18 dB to Mute P1 7- Bit ADC R2 CVOL Tone Generator and Mixer Are NOT Shown 24 dB to Mute Volume Level Register Controlled AVSS B0210-08 Figure 5-17.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is concentrated in the low-frequency region of the input signal.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.4.2 www.ti.com DRC Hysteresis DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be programmed to represent values between 0 dB and 3 dB in steps of 1 dB. DRC hysteresis provides a programmable window around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled, or the enabled DRC to become disabled.
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TLV320DAC3100 www.ti.com 5.5.4.6 • • • • • • SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Example Setup for DRC Digital Vol gain = 12 dB Threshold = –24 dB Hysteresis = 3 dB Hold time = 0 ms Attack rate = 1.9531e–4 dB per sample period Decay rate = 2.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com This feature is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections due to mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is provided. This can be programmed via page 0 / register 67, bits D4–D2.
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TLV320DAC3100 www.ti.com 5.5.7 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) A special algorithm has been included in the digital signal processing block PRB_P25 for generating a digital sine-wave signal that is sent to the DAC. The digital sine-wave generator is also referred to as the beep generator in this document. This functionality is intended for generating key-click sounds or beeps for user feedback.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com NOTES: 1. fin should be less than fS/4. 2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused MSBs must be written as 0s. 3. For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs must be written as 0s.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Play - Paused Volume Ramp Down Soft Mute DAC Volume Ramp Down WAIT Time (A) Wait (A) ms For fS = 32 kHz ® Wait 25 ms (min) For fS = 48 kHz ® Wait 20 ms (min) DAC Power Down Update Digital Filter Coefficients DAC Volume Ramp Up Time (B) For fS = 32 kHz ® 25 ms For fS = 48 kHz ® 20 ms DAC Power UP Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Play - Continue F0024-02 Figure 5-19.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.11 Analog Audio Routing The TLV320DAC3100 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels. The TLV320DAC3100 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-24. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) Register Value (D6–D0) (1) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) 0 0.0 30 –15.0 60 –30.1 90 –45.2 1 –0.5 31 –15.5 61 –30.6 91 –45.8 2 –1.0 32 –16.0 62 –31.1 92 –46.2 3 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2.0 34 –17.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.12 Analog Outputs Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, Figure 1-1. 5.5.12.1 Headphone Drivers The TLV320DAC3100 features a stereo headphone driver (HPL and HPR) that can deliver up to 30 mW per channel, at 3.3-V supply voltage, into a 16-Ω load.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The TLV320DAC3100 has a short-circuit protection feature for the speaker driver that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker-driver output stage.) In case of a short circuit, the output is disabled and a status flag is provided as a read-only bit on page 1 / register 32, bit D0.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com In all cases, DOSR is limited in its range by the following condition: 2.8 MHz < DOSR × DAC_fS < 6.2 MHz Based on the identified filter type and the required signal-processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25).
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 3. Program analog blocks (a) Set register page to 1 (b) Program common-mode voltage (c) Program headphone-specific de-pop settings (in case headphone driver is used) (d) Program routing of DAC output to the output amplifier (headphone/lineout or speaker) (e) Unmute and set gain of output drivers (f) Power up output drivers 4.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.
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TLV320DAC3100 www.ti.com # w # # w # w # # # # w 5.6 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Powerup DAC left and right channels (soft step enabled) 30 3F D4 DAC Left gain = -22 dB 30 41 D4 DAC Right gain = -22 dB 30 42 D4 (c) Unmute digital volume control Unmute DAC left and right channels 30 40 00 CLOCK Generation and PLL The TLV320DAC3100 supports a wide range of options for generating clocks for the DAC section as well as interface and other control blocks, as shown in Figure 5-20.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com BCLK MCLK DIN GPIO1 PLL_CLKIN PLL ´ (R ´ J.D)/P BCLK MCLK GPIO1 PLL_CLK CODEC_CLKIN ¸ NDAC To DAC MAC NDAC = 1, 2, ..., 127, 128 DAC_CLK ¸ MDAC MDAC = 1, 2, ..., 127, 128 DAC_MOD_CLK ¸ DOSR DOSR = 1, 2, ..., 1023, 1024 DAC_fS B0357-04 Figure 5-20. Clock Distribution Tree DAC _ MOD _ CLK = DAC _ fS = CODEC _ CLKIN NDAC ´ MDAC CODEC _ CLKIN NDAC ´ MDAC ´ DOSR (5) Table 5-26.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel, DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shutdown.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com PLL_CLK MCLK BCLK DIN DAC_MOD_CLK DAC_CLK CDIV_CLKIN M = 1, 2, ..., 127, 128 ÷M GPIO1 (CLKOUT) B0363-01 Figure 5-22. General-Purpose Clock Output Options Table 5-27. Maximum TLV320DAC3100 Clock Frequencies DVDD ≥ 1.65 V Clock CODEC_CLKIN ≤ 110 MHz DAC_CLK (DAC processing clock) ≤ 49.152 MHz DAC_MAC_CLK ≤ 49.152 MHz with DRC disabled ≤ 48 MHz with DRC enabled DAC_MOD_CLK 6.758 MHz DAC_fS 0.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 / register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is programmed into two registers.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-28. PLL Example Configurations (continued) PLL_CLKIN (MHz) PLLP PLLR PLLJ PLLD MDAC NDAC DOSR 4 1 7 1680 7 2 128 fS = 44.1 kHz 48 5.6.2 Timer The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce logics and interrupts. The MCLK divider must be set such a way that the divider output is ~1 MHz for the timers to be closer to the programmed value.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The TLV320DAC3101 also includes a feature to offset the position of start-of-data-transfer with respect to the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in page 0 / register 28. The TLV320DAC3101 also has the feature of inverting the polarity of the bit clock used for transferring the audio data as compared to the default clock polarity used.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 3 LD(n) 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data LD(n+1) RD(n) = n'th sample of right channel data Figure 5-25.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-28.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 0 N N N - - 1 2 3 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD (n+1) RD(n) = n'th sample of right channel data Figure 5-31.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-29.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com S_BCLK BCLK BCLK BCLK BCLK_OUT BCLK_INT S_BCLK WCLK S_WCLK WCLK WCLK DAC_fS Primary Audio Processor DAC_WCLK_INT S_WCLK Audio Digital Serial Interface DIN DOUT DIN DIN_INT S_DIN DIN BCLK2 GPIO1 S_BCLK BCLK BCLK BCLK_OUT WCLK2 GPIO1 S_WCLK WCLK WCLK BCLK_OUT DAC_fS Secondary Audio Processor GPIO1 DAC_fS Clock Generation S_DIN DOUT DIN B0375-01 Figure 5-34. Audio Serial Interface Multiplexing 5.7.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320DAC3100 can only act as a slave device. An I2C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) DA(6) RA(0) 8-bit Register Address (M) Slave Ack (S) Repeat Start (M) DA(0) 7-bit Device Address (M) D(7) Read (M) Slave Ack (S) 8-bit Register Data (S) D(0) Master No Ack (M) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-36.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 6 REGISTER MAP 6.1 TLV320DAC3100 Register Map All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are available for reading only. The TLV320DAC3100 contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 3 (0x03): OT FLAG D7–D2 D1 READ/ WRITE R R RESET VALUE XXXX XX 1 D0 R X BIT DESCRIPTION Reserved. Do not write to these bits. 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up 1: Normal operation Reserved. Do not write to this bit.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 8 (0x08): PLL D-Value LSB (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION PLL fractional multiplier D-value LSBs D[7:0] Note that page 0 / register 8 must be written immediately after page 0 / register 7.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 29 (0x1D): Codec Interface Control 2 D7–D4 D3 READ/ WRITE R/W R/W RESET VALUE 0000 0 D2 R/W 0 D1–D0 R/W 00 BIT DESCRIPTION Reserved 0: BCLK is not inverted (valid for both primary and secondary BCLK). 1: BCLK is inverted (valid for both primary and secondary BCLK).
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 39 (0x27): Overflow Flags D7 (1) READ/ WRITE R RESET VALUE 0 D6 (1) R 0 D5 (1) R 0 D4–D0 R 0 0000 BIT (1) DESCRIPTION Left-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. Right-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. DAC Barrel Shifter Output Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 50 (0x32): Reserved READ/ WRITE R RESET VALUE 0000 0000 D7–D6 D5–D2 READ/ WRITE R/W R/W RESET VALUE XX 0000 D1 D0 R R/W X 0 READ/ WRITE R RESET VALUE XXXX XXXX READ/ WRITE R RESET VALUE 0000 0000 D7–D3 D2–D1 READ/ WRITE R/W R/W RESET VALUE 0000 0 01 D0 R X READ/ WRITE R RESET VALUE XXXX XXXX BIT D7-D0 DESCRIPTION Reserved. Do not use.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 60 (0x3C): DAC Processing Block Selection READ/ WRITE R/W R/W RESET VALUE 000 0 0001 READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 01 D3–D2 R/W 01 D1–D0 R/W 00 D7–D4 D3 READ/ WRITE R/W R/W RESET VALUE 0000 1 D2 R/W 1 D1–D0 ( R/W 00 BIT D7–D5 D4–D0 DESCRIPTION Reserved. Write only default value. 0 0000: Reserved. Do not use.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 65 (0x41): DAC Left Volume Control READ/ WRITE R/W RESET VALUE 0000 0000 READ/ WRITE R/W RESET VALUE 0000 0000 D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R XX D4–D2 R/W 000 D1–D0 R/W 00 BIT D7–D0 DESCRIPTION Left DAC Channel Digital Volume Control Setting 0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 68 (0x44): DRC Control 1 D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 R/W 0 D4–D2 R/W 011 D1–D0 R/W 11 D7 D6–D3 READ/ WRITE R R/W RESET VALUE 0 0111 D2–D0 R 000 READ/ WRITE R/W RESET VALUE 0000 BIT DESCRIPTION Reserved. Write only the reset value to these bits.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 71 (0x47): Left Beep Generator D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D0 R/W R/W 0 00 0000 BIT (1) (1) DESCRIPTION 0: Beep generator is disabled. 1: Beep generator is enabled (self-clearing based on beep duration). Reserved. Write only reset value.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 79 (0x4F): Beep Cos(x) LSB READ/ WRITE R/W RESET VALUE 1110 0011 READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3 D2–D0 R/W R/W 0 000 READ/ WRITE R R RESET VALUE 0 XXX XXXX BIT D7–D0 DESCRIPTION 8 LSBs out of 16 bits for cos(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate.
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TLV320DAC3100 www.ti.com 6.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 1: DAC, Power-Controls and MISC Logic-Related Programmabilities Page 1 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 0111 D2–D1 R/W 11 D0 R/W 0 D7 D6–D4 READ/ WRITE R/W R/W RESET VALUE 0 000 D3–D0 R/W 0000 BIT DESCRIPTION 0: If power-down sequence is activated by device software, power down using page 1 / register 46, bit D7, then power down the DAC simultaneously with the HP and SP amplifiers.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing D7–D6 READ/ WRITE R/W RESET VALUE 00 D5 R/W 0 BIT D4 0 D3–D2 R/W 00 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 DESCRIPTION 00: DAC_L is not routed anywhere. 01: DAC_L is routed to the left-channel mixer amplifier. 10: DAC_L is routed directly to the HPL driver.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 40 (0x28): HPL Driver D7 D6–D3 READ/ WRITE R/W R/W RESET VALUE 0 0000 D2 R/W 0 D1 R/W 1 D0 R 0 BIT (1) DESCRIPTION Reserved. Write only zero to this bit. 0000: HPL driver PGA = 0 dB 0001: HPL driver PGA = 1 dB 0010: HPL driver PGA = 2 dB ... 1000: HPL driver PGA = 8 dB 1001: HPL driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits. 0: HPL driver is muted.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 1 / Register 44 (0x2C): HP Driver Control D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D3 R/W 00 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT (1) DESCRIPTION Debounce Time for Headset Short-Circuit Detection MCLK/DIV (Page 3 / (1) register 16) = 1-MHz Internal Oscillator Source Source 000: Debounce time = 0 μs 0 μs 001: Debounce time = 8 μs 7.8 μs 010: Debounce time = 16 μs 15.6 μs 011: Debounce time = 32 μs 31.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved BIT D7–D0 6.4 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Write only the reset value to these bits. Control Registers, Page 3: MCLK Divider for Programmable Delay Timer Default values shown for this page only become valid 100 μs following a hardware or software reset.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 8 / Register 1 (0x01): DAC Coefficient RAM Control D7–D3 D2 READ/ WRITE R/W R/W RESET VALUE 0000 0 0 D1 R 0 D0 R/W 0 BIT DESCRIPTION Reserved. Write only the reset value.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-2.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-2.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-2.
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TLV320DAC3100 www.ti.com 6.6 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127) Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 9 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 6.7 www.ti.com Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63) Table 6-4. Page 12 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-5.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-5.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-5. Page-12 DAC Buffer B Registers (continued) REGISTER NUMBER RESET VALUE 122 (0x7A) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad F 123 (0x7B) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad F 124 (0x7C) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad F 125 (0x7D) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad F 126–127 0000 0000 Reserved 6.
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TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-7.
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TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February, 2010) to Revision A • • • • • • • • • • • • • Page Changed register 36 to register 35 in section 5.4.2. ....................................................................... Deleted Analog Volume Control for Headphone and Speaker Outputs (for D7=0) table and added table note to D7=1 table. .
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320DAC3100IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC3100IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC3100IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320DAC3100IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320DAC3100IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320DAC3100IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320DAC3100IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.