Datasheet

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FEATURES

DESCRIPTION

TLV320DAC32

www.ti.com

........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008

LOW POWER STEREO AUDIO DAC FOR PORTABLE AUDIO/TELEPHONY

• Stereo Audio DAC

– 95-dBA Signal-to-Noise Ratio

The TLV320DAC32 is a low power stereo audio DAC

with and integrated power amplifier designed to drive

– 16/20/24/32-Bit Data

stereo headphones or speakers. This device also has

– Supports Rates From 8 kHz to 96 kHz

a pair of analog inputs which allow routing of external

– 3D/Bass/Treble/EQ/De-emphasis Effects

signals to the output amplifiers. The playback path

includes a mix/mux capability from the stereo DAC

• Two Audio Input Pins

and analog inputs, through programmable volume

– Allows Analog Bypass Path

controls, to the headphone outputs. Extensive

• Four Audio Output Drivers

stereo 96-kHz playback as low as 20mW from a

– Stereo 8- Ω , 500-mW/Channel Speaker Drive

3.3-V analog supply, making it ideal for portable

Capability

battery-powered audio and telephony applications.

– Stereo Fully Differential or Single-Ended

The TLV320DAC32 contains four high-power output

Headphone Drivers

drivers. These drivers are capable of driving a variety

• Low Power: 18-mW Stereo 48-kHz Playback

of load configurations, including up to four channels

With 3.3-V Analog Supply

of single-ended 16- Ω headphones using ac-coupling

• Programmable Input/Output Analog Gains

capacitors, or stereo 16- Ω headphones in a cap-less

output configuration. In addition, pairs of drivers can

• Programmable Microphone Bias Level

be used to drive 8- Ω speakers in a BTL configuration

• Headphone Jack Detection

at 500 mW per channel.

• Programmable PLL for Flexible Clock

The stereo audio DAC supports sampling rates from

Generation

8-kHz to 96-kHz and includes programmable digital

• I

C Control Bus

filtering in the DAC path for 3D, bass, treble,

• Audio Serial Data Bus Supports I

midrange effects, speaker equalization, and

Left/Right-Justified, DSP, and TDM Modes

de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz rates.

• Extensive Modular Power Control

The serial control bus uses the I2C protocol, while the

serial audio data bus is programmable for I2S,

• Internal Selectable LDO Allows Operation

left/right-justified, DSP, or TDM modes. A highly

From Single 3.3-V Supply

programmable PLL is included for flexible clock

• Power Supplies:

generation and support for all standard audio rates

– Analog: 2.7 V – 3.6 V.

from a wide range of available MCLKs, varying from

512-kHz to 50-MHz, with special attention paid to the

– Digital Core: 1.525 V – 1.95 V

most popular cases of 12-MHz, 13-MHz, 16-MHz,

– Digital I/O: 1.1 V – 3.6 V

19.2-MHz, and 19.68-MHz system clocks.

• Package: 5 נ 5 mm 32-QFN

The TLV320DAC32 operates from analog supplies of

2.7 V – 3.6 V, a digital core supply of 1.525 V – 1.95

V, and a digital I/O supply of 1.1 V – 3.6 V. An

internal LDO regulator allows the device to internally

generate the lower voltage power supply needed for

digital core logic, thereby allowing full operation from

a single 3.3-V supply voltage.

The TLV320DAC32 is a software-compatible subset

of the existing TLV320AIC32 and TLV320AIC33

audio codecs, allowing simple transition from a

system with record and playback to a system with

playback only.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (70 pages)

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TLV320DAC32 www.ti.com........................................................................................................................................
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The device is available in a 5 x 5mm 32-lead QFN package.
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TLV320DAC32 www.ti.com........................................................................................................................................
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) AVDD_DAC, DRVDD (1) Analog supply voltage DVDD (1) Digital core supply voltage IOVDD (1) Digital I/O supply voltage VI Analog full-scale 0-dB input voltage (DRVDD = 3.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TIMING CHARACTERISTICS (1) All specifications typical at 25C, DVDD = 1.8 V IOVDD = 1.1 V PARAMETER MIN IOVDD = 3.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TIMING CHARACTERISTICS (continued) All specifications typical at 25C, DVDD = 1.8 V IOVDD = 1.1 V PARAMETER MIN IOVDD = 3.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs POWER (HPLOUT Differential 16.2 Ω) TOTAL HARMONIC DISTORTION vs POWER (HPROUT Differential 16.2 Ω) 0 0 -20 -30 -40 -50 -60 -70 VDD = 3.6 V, VCM = 1.8 V -80 VDD = 2.7 V, VCM = 1.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs POWER (HPLCOM - HPRCOM Differential 8.2 Ω) MIC BIAS VOLTAGE vs SUPPLY VOLTAGE 3.5 VDD = 3.3 V, VCM = 1.65 V VDD = 2.7 V, VCM = 1.35 V -10 AVDD 3 -20 2.5 V 2.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION Multimedia Processor IOVDD R AVDD_DAC DRVDD DRVDD DIN BCLK WCLK MCLK SDA RESET AVDD (2.7V-3.6V) SCL R 0.1 mF 1 mF 0.1 mF 1 mF 0.1 mF 10 mF 1 mF A TLV320DAC32 HPLOUT 8 ohm HPLCOM MICBIAS HPRCOM/SPKFC 0.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Multimedia Processor IOVDD R AVDD_DAC DRVDD DRVDD DIN BCLK WCLK MCLK SDA RESET AVDD (2.7V-3.6V) SCL R 0.1 mF 1 mF 0.1 mF 10 mF 1 mF 0.1 mF 1 mF A TLV320DAC32 HPLOUT 8 ohm HPLCOM MICBIAS HPRCOM/SPKFC 8 ohm 0.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) Multimedia Processor IOVDD R DIN BCLK WCLK MCLK SDA RESET AVDD (2.7V-3.6V) SCL R AVDD_DAC DRVDD DRVDD 0.1 mF 1 mF 0.1 mF 10 mF 1 mF 0.1 mF 1 mF A TLV320DAC32 HPLOUT 16 ohm HPLCOM MICBIAS HPRCOM/SPKFC 0.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Multimedia Processor IOVDD R AVDD_DAC DRVDD DRVDD DIN BCLK WCLK MCLK SDA RESET AVDD (2.7V-3.6V) SCL R 0.1 mF 1 mF 0.1 mF 1 mF 10 mF 1 mF 0.1 mF A TLV320DAC32 HPLOUT 16 ohm HPLCOM MICBIAS HPRCOM/SPKFC 0.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) Multimedia Processor IOVDD R DIN BCLK WCLK MCLK SDA RESET AVDD (2.7V-3.6V) SCL R AVDD_DAC DRVDD DRVDD 0.1 mF 1 mF 0.1 mF 1 mF 10 mF 1 mF 0.1 mF A TLV320DAC32 HPLOUT 16 ohm HPLCOM 8 ohm MICBIAS A HPRCOM/SPKFC 0.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Multimedia Processor IOVDD R AVDD_DAC DRVDD DRVDD DIN BCLK WCLK MCLK SDA RESET AVDD (2.7V-3.6V) SCL R 0.1 mF 1 mF 0.1 mF 1 mF 10 mF 1 mF 0.1 mF A TLV320DAC32 HPLOUT 16 ohm HPLCOM 8 ohm MICBIAS A HPRCOM/SPKFC 0.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 OVERVIEW The TLV320DAC32 is a highly flexible, low power stereo audio DAC with extensive feature integration, intended for application in smartphones, PDAs, and portable computing, communication, and entertainment applications.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TLV320DAC32 LDO = OFF IOVDD 3.3V LDO_SELECT IOVDD DVDD 1.8V 1 mF 0.1 mF DVDD 0.1 mF 1 mF IOVSS D A. See tables for voltage range of DVDD and IOVDD Figure 22.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access registers in page 1.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 DIGITAL AUDIO DATA SERIAL INTERFACE Audio data is transferred between the host processor and the TLV320DAC32 via the digital audio data serial interface, or “audio bus”.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com n-1 n-2 n-3 n-1 n-2 n-3 Figure 27. Left Justified Serial Data Bus Mode Operation I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TDM DATA TRANSFER Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com MCLK BCLK CLKDIV_CLKIN PLL_CLKIN CLKDIV_IN PLL_IN Q = 3,3, . . . . ,16,17 K = J.D J = 1,2,3,. . . , 62,63 D= 0000,0001, . . . ,9998,9999 R= 1,2,3,4, . . . ,15,16 P= 1,2, . . . .
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4 P, R, J, and D are register programmable.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com 16.0 1 1 6 1440 48000.00 0.0000 19.2 1 1 5 1200 48000.00 0.0000 19.68 1 1 4 9951 47999.79 0.0004 48.0 4 1 8 1920 48000.00 0.0000 STEREO AUDIO DAC The TLV320DAC32 includes a stereo audio DAC supporting sampling rates from 8-kHz to 96-kHz.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 LB1 LB2 RB1 RB2 Figure 32. Structure of the Digital Effects Processing for Independent Channel Processing The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com L LB2 TOLEFTCHANNEL TO LEFT CHANNEL LB1 Atten RB2 R TO CHANNEL TO RIGHT RIGHT CHANNEL Figure 33. Architecture of the Digital Audio Processing When 3-D Effects are Enabled It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 AUDIO DAC DIGITAL VOLUME CONTROL The audio DAC includes a digital volume control block which implements a programmable digital gain. The volume level can be varied from 0-dB to –63.5-dB in 0.5-dB steps, in addition to a mute bit, independently for each channel.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com AUDIO ANALOG INPUTS The TLV320DAC32 includes two single-ended audio inputs that are sent to an output mixer with volume control capability. By configuring the mixer to accept multiple inputs, an analog mixing function occurs.
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TLV320DAC32 www.ti.com........................................................................................................................................
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com The device includes a further option that falls between the other two – while it requires less power drawn while the output drivers are in power down, it also takes a slightly longer delay to power-up without artifact than if the bandgap reference is kept powered up.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 AVDD MICBIAS LINER MIC AMP Stereo g s To Detection Block LINEL To Mixer s TLV320DAC32 Cellular g m Stereo + Cellular g m s s s HPLOUT m = mic s = stereo g = ground/vgnd HPROUT PWR AMP PWR AMP To Detection Block HPRCOM HPLCOM PWR AMP 1.35V Figure 35.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com AVDD MICBIAS LINER MIC AMP Stereo g s To Detection Block LINEL To Mixer s TLV320DAC32 Cellular g m Stereo + Cellular g m s s A s HPLOUT m = mic s = stereo g = ground/vgnd HPROUT PWR AMP PWR AMP Figure 36.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 Differential Headphone Connector Assembly TLV320DAC32 SW1 A LINER To Detection Block HPLOUT PWR AMP HPLCOM PWR AMP HPRCOM PWR AMP HPROUT PWR AMP Figure 37. Configuration of device for jack detection using a fully differential stereo headphone output connection.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 1: BIT READ/ WRITE RESET VALUE D7 W 0 D6–D0 W 0000000 DESCRIPTION Software Reset Bit 0 : Don’t Care 1 : Self clearing software reset Reserved. Do not write to these bits.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 Page 0 / Register 4: BIT READ/ WRITE RESET VALUE D7–D2 R/W 000001 D1–D0 R/W 00 DESCRIPTION PLL J Value 000000: Reserved, do not write this sequence 000001: J = 1 000010: J = 2 000011: J = 3 … 111110: J = 62 111111: J = 63 Reserved, write only zeros to these bits Table 1.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 11: BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D6 R 0 Reserved. Only write zeroes to these bits. D5 R 0 Left DAC Overflow Flag This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed.
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TLV320DAC32 www.ti.com........................................................................................................................................
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 Page 0 / Register 40: High Power Output Stage Control Register (continued) BIT READ/ WRITE RESET VALUE DESCRIPTION D3–D2 R/W 00 LINER Bypass Path Control 00: LINER bypass is disabled 01: LINER bypass uses LINER 10: Reserved. Do not write this sequence to these register bits. 11: Reserved.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 43: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W Left DAC Digital Volume Control Register DESCRIPTION Left DAC Digital Mute 0: The left DAC channel is not muted 1: The left DAC channel is muted 0000000 Left DAC Digital Volume Control Setting 0000000: Gain = 0.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 Table 5. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 15 -7.5 45 -22.6 75 -37.7 105 -52.7 16 -8.0 46 -23.1 76 -38.2 106 -53.7 17 -8.5 47 -23.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 0 / Register 49: BIT READ/ WRITE RESET VALUE D7-D0 R/W 00000000 DESCRIPTION Reserved. Do not write to this register.
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TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 Page 1 / Register 0: BIT READ/ WRITE RESET VALUE D7-D1 X 0000000 D0 R/W 0 DESCRIPTION Reserved, write only zeros to these register bits Page Select Bit Writing zero to this bit sets Page-0 as the active page for following register accesses.
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TLV320DAC32 SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com Page 1 / Register 55–127: 62 BIT READ/ WRITE RESET VALUE D7-D0 R 00000000 Reserved Registers DESCRIPTION Reserved. Do not write to these registers.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320DAC32IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC32IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320DAC32IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TLV320DAC32IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.