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TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Four 10-Bit D/A Converters

Programmable Settling Time

of 3 µs or 9 µs Typ

TMS320, (Q)SPI, and Microwire

Compatible Serial Interface

Internal Power-On Reset

Low Power Consumption:

5.5 mW, Slow Mode – 5-V Supply

3.3 mW, Slow Mode – 3-V Supply

Reference Input Buffers

Voltage Output Range ...2× the Reference

Input Voltage

Monotonic Over Temperature

Dual 2.7-V to 5.5-V Supply (Separate Digital

and Analog Supplies)

Hardware Power Down (10 nA)

Software Power Down (10 nA)

Simultaneous Update

applications

Battery Powered Test Instruments

Digital Offset and Gain Adjustment

Industrial Process Controls

Machine and Motion Control Devices

Communications

Arbitrary Waveform Generation

description

The TLV5604 is a quadruple 10-bit voltage output

digital-to-analog converter (DAC) with a flexible

4-wire serial interface. The 4-wire serial interface

allows glueless interface to TMS320, SPI, QSPI,

and Microwire serial ports. The TLV5604 is

programmed with a 16-bit serial word comprised

of a DAC address, individual DAC control bits, and

a 10-bit DAC value.

The device has provision for two supplies: one digital supply for the serial interface (via pins DV

and DGND),

and one for the DACs, reference buffers and output buffers (via pins AV

and AGND). Each supply is

independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical

application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins

and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be

tied together.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode

makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to

allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits

within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD

terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow

DACs A and B to have a different reference voltage then DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The

TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from

–40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

LDAC

DIN

SCLK

DGND

REFINAB

OUTA

OUTB

OUTC

OUTD

REFINCD

AGND

(TOP VIEW)

D OR PW PACKAGE

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

Summary of content (31 pages)

PAGE 1
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 D D D D D D D D D Four 10-Bit D/A Converters Programmable Settling Time of 3 µs or 9 µs Typ TMS320, (Q)SPI, and Microwire Compatible Serial Interface Internal Power-On Reset Low Power Consumption: 5.5 mW, Slow Mode – 5-V Supply 3.3 mW, Slow Mode – 3-V Supply Reference Input Buffers Voltage Output Range . . .
PAGE 2
TLV5604 2.7-V TO 5.
PAGE 3
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 9 AVDD CS 16 DGND 8 DIN 4 DVDD 1 FS 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5604. PD 2 I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
PAGE 4
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 recommended operating conditions Supply voltage voltage, AVDD, DVDD High level digital input voltage High-level voltage, VIH Low level digital input voltage, Low-level voltage VIL Reference voltage, voltage Vreff to REFINAB REFINAB, REFINCD terminal MIN NOM 5-V supply 4.5 5 5.5 3-V supply 2.7 3 3.3 DVDD = 2.7 V 2 DVDD = 5.5 V 2.4 MAX UNIT V V DVDD = 2.
PAGE 5
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) individual DAC output specifications PARAMETER VO TEST CONDITIONS Voltage output MIN RL = 10 kΩ Output load regulation accuracy TYP 0 MAX AVDD–0.4 UNIT V 0.1 0.
PAGE 6
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) analog output dynamic performance PARAMETER SR Output slew rate TEST CONDITIONS CL = 100 pF, RL = 10 kΩ, VO = 10% to 90% 90%, Vref = 2.048 V, 1024 V MIN TYP MAX UNIT Fast 5 V/µs Slow 1 V/µs ts Output settling time To ± 0.
PAGE 7
TLV5604 2.7-V TO 5.
PAGE 8
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 TYPICAL CHARACTERISTICS LOAD REGULATION LOAD REGULATION 0.35 0.20 VDD = 5 V, VREF = 2 V, VO = Full Scale 0.16 VO – Output Voltage – V VO – Output Voltage – V 0.30 VDD = 3 V, VREF = 1 V, VO = Full Scale 0.18 0.25 5 V Slow Mode, Sink 0.20 5 V Fast Mode, Sink 0.15 0.10 0.14 3 V Slow Mode, Sink 0.12 0.10 3 V Fast Mode, Sink 0.08 0.06 0.04 0.05 0.02 0 0 0 0.02 0.
PAGE 9
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 4 4 VDD = 3 V, VREF = 1.024 V, VO = Full Scale 3.5 Fast Mode Fast Mode I DD – Supply Current – mA I DD – Supply Current – mA 3.5 3 2.5 2 1.5 3 2.5 2 Slow Mode 1.5 Slow Mode 1 VDD = 5 V, VREF = 1.024 V, VO = Full Scale 1 0.5 –40 –20 0 20 40 60 T – Temperature – °C 80 0.
PAGE 10
TLV5604 2.7-V TO 5.
PAGE 11
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 0.2 VDD = 5 V, Vref = 2 V, CLK = 1 MHz 0 –0.2 –0.4 –0.6 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Digital Code DNL – Differential Nonlinearity – LSB Figure 13 DIFFERENTIAL NONLINEARITY 0.15 VDD = 5 V, Vref = 2 V, CLK = 1 MHz 0.1 0.05 0 –0.05 –0.
PAGE 12
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION general function The TLV5604 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer.
PAGE 13
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5604 to a TMS320, SPI, or Microwire port using only three pins.
PAGE 14
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION In power down mode, all amplifiers within the TLV5604 are disabled. A particular DAC (A, B, C, D) of the TLV5604 is selected by A1 and A0 within the input word. A1 A0 DAC 0 0 A 0 1 B 1 0 C 1 1 D TLV5604 interfaced to TMS320C203 DSP Hardware interfacing Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP.
PAGE 15
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––; ; Processor: TMS320C203 runnning at 40 MHz; ; Description: ; ; This program generates a differential in-phase (sine) on (OUTA–OUTB) and it’s ; quadrature (cosine) as a differential signal on (OUTC–OUTD).
PAGE 16
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION .word 00AE9h .word 0097Ch .word 00800h .word 00684h .word 00517h .word 003C6h .word 0029Fh .word 001ADh .word 000F9h .word 0008Ah .word 00064h .word 0008Ah .word 000F9h .word 001ADh .word 0029Fh .word 003C6h .word 00517h .word 00684h .word 00800h .word 0097Ch .word 00AE9h .word 00C3Ah .word 00D61h .word 00E53h .word 00F07h .word 00F76h .word 00F9Ch .
PAGE 17
TLV5604 2.7-V TO 5.
PAGE 18
TLV5604 2.7-V TO 5.
PAGE 19
TLV5604 2.7-V TO 5.
PAGE 20
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION TLV5604 interfaced to MCS51 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5604 to an MCS51 Microcontroller. The serial DAC input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line.
PAGE 21
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 APPLICATION INFORMATION ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Processor: 80C51 ; ; Description: ; ; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s ; quadrature (cosine) as a differential signal on (OUTC–OUTD).
PAGE 22
TLV5604 2.7-V TO 5.
PAGE 23
TLV5604 2.7-V TO 5.
PAGE 24
TLV5604 2.7-V TO 5.
PAGE 25
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.
PAGE 26
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX 0,10 PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2009 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5604CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV5604CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV5604IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5604CDR SOIC D 16 2500 346.0 346.0 33.0 TLV5604CPWR TSSOP PW 16 2000 346.0 346.0 29.0 TLV5604IPWR TSSOP PW 16 2000 346.0 346.0 29.
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