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TLV5614

2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Four 12-Bit D/A Converters

D Programmable Settling Time of Either 3 µs

or 9 µs Typ

D TMS320, (Q)SPI, and Microwire

Compatible Serial Interface

D Internal Power-On Reset

D Low Power Consumption:

8 mW, Slow Mode – 5-V Supply

3.6 mW, Slow Mode – 3-V Supply

D Reference Input Buffer

D Voltage Output Range ...2× the Reference

Input Voltage

D Monotonic Over Temperature

D Dual 2.7-V to 5.5-V Supply (Separate Digital

and Analog Supplies)

D Hardware Power Down (10 nA)

D Software Power Down (10 nA)

D Simultaneous Update

applications

D Battery Powered Test Instruments

D Digital Offset and Gain Adjustment

D Industrial Process Controls

D Machine and Motion Control Devices

D Communications

D Arbitrary Waveform Generation

description

The TLV5614 is a quadruple 12-bit voltage output

digital-to-analog converter (DAC) with a flexible

4-wire serial interface. The 4-wire serial interface

allows glueless interface to TMS320, SPI, QSPI,

and Microwire serial ports. The TLV5614 is

programmed with a 16-bit serial word comprised

of a DAC address, individual DAC control bits, and

a 12-bit DAC value. The device has provision for

two supplies: one digital supply for the serial

interface (via pins DV

and DGND), and one for

the DACs, reference buffers, and output buffers (via pins AV

and AGND). Each supply is independent of the

other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the

DAC is controlled via a microprocessor operating on a 3 V supply (also used on pins DV

and DGND), with

the DACs operating on a 5 V supply. Of course, the digital and analog supplies can be tied together.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode

makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to

allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits

within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD

terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow

DACs A and B to have a different reference voltage then DACs C and D.

The TLV5614 is implemented with a CMOS process and is available in a 16-terminal SOIC package. The

TLV5614C is characterized for operation from 0°C to 70°C. The TLV5614I is characterized for operation from

–40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

LDAC

DIN

SCLK

DGND

REFINAB

OUTA

OUTB

OUTC

OUTD

REFINCD

AGND

(TOP VIEW)

D OR PW PACKAGE

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

Summary of content (34 pages)

PAGE 1
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 D Four 12-Bit D/A Converters D Programmable Settling Time of Either 3 µs D D D D D D or 9 µs Typ TMS320, (Q)SPI, and Microwire Compatible Serial Interface Internal Power-On Reset Low Power Consumption: 8 mW, Slow Mode – 5-V Supply 3.6 mW, Slow Mode – 3-V Supply Reference Input Buffer Voltage Output Range . . .
PAGE 2
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 AVAILABLE OPTIONS PACKAGE WSP† (YE) TA SOIC (D) TSSOP (PW) 0°C to 70°C TLV5614CD TLV5614CPW ––– – 40°C to 85°C TLV5614ID TLV5614IPW † Wafer Scale Packaging, also called Bumped Dice. See Figure 17.
PAGE 3
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 Terminal Functions TERMINAL NAME NO. AGND 9 AVDD CS 16 DGND 8 DIN 4 DVDD 1 6 I/O DESCRIPTION Analog ground Analog supply I Chip select. This terminal is active low. Digital ground I Serial data input Digital supply 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5614.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 recommended operating conditions Supply voltage voltage, AVDD, DVDD High level digital input voltage, High-level voltage VIH Low level digital input voltage, Low-level voltage VIL Reference voltage, voltage Vref to REFINAB, REFINAB REFINCD terminal MIN NOM MAX 5-V supply 4.5 5 5.5 3-V supply 2.7 3 3.3 DVDD = 2.7 V 2 DVDD = 5.5 V 2.4 0.6 DVDD = 5.
PAGE 5
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) (continued) individual DAC output specifications PARAMETER VO TEST CONDITIONS Voltage output range MIN RL = 10 kΩ Output load regulation accuracy TYP 0 RL = 2 kΩ vs 10 kΩ MAX AVDD–0.4 UNIT V 0.1 0.
PAGE 6
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) (continued) analog output dynamic performance PARAMETER SR Output slew rate TEST CONDITIONS CL = 100 pF, RL = 10 kΩ, 90% VO = 10% to 90%, Vref = 2.048 V, 1024 V MIN TYP MAX UNIT Fast 5 V/µs Slow 1 V/µs 3 5.
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TLV5614 2.7-V TO 5.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS LOAD REGULATION LOAD REGULATION 0.2 0.35 VDD = 3 V, Vref = 1 V, VO = Full Scale 0.18 0.16 0.30 0.25 VO – Output – V 0.14 VO – Output – V VDD = 5 V, Vref = 2 V, VO = Full Scale 3 V Slow Mode, Sink 0.12 0.10 3 V Fast Mode, Sink 0.08 0.06 5 V Slow Mode, Sink 0.20 5 V Fast Mode, Sink 0.15 0.10 0.04 0.05 0.02 0 0 0 0.01 0.02 0.05 0.1 0.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 4 3.5 I DD – Supply Current – mA 3.5 I DD – Supply Current – mA 4 VDD = 3 V, Vref = 1.024 V, VO Full Scale (Worst Case For IDD) Fast Mode 3 2.5 2 1.5 1 3 –20 VDD = 5 V, Vref = 1.024 V, VO Full Scale (Worst Case For IDD) 2.5 2 1.5 Slow Mode 0.
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TLV5614 2.7-V TO 5.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY 0.3 0.25 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 –0.25 –0.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION general function The TLV5614 is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5614 to a TMS320, SPI, or Microwire port using only three pins.
PAGE 14
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION In power-down mode, all amplifiers within the TLV5614 are disabled. A particular DAC (A, B, C, D) of the TLV5614 is selected by A1 and A0 within the input word. A1 A0 DAC 0 0 A 0 1 B 1 0 C 1 1 D Using TLV5614IYE, Bumped Dice D Melting point of eutectic solder is 183°C.
PAGE 15
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 TLV5614 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example of how to connect the TLV5614 to a TMS320C203 DSP. The serial port is configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the TLV5614. Data is transmitted on the DX line, with the serial clock input on the CLKX line.
PAGE 16
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Processor: TMS320C203 runnning at 40 MHz ; ; Description: ; ; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s ; quadrature (cosine) as a differential signal on (OUTC–OUTD).
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Main Program ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– .ps 1000h .
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TLV5614 2.7-V TO 5.
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TLV5614 2.7-V TO 5.
PAGE 21
TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION TLV5614 interfaced to MCS51 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5614 to an MCS51 Microcontroller. The serial DAC input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line.
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TLV5614 2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003 APPLICATION INFORMATION ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Processor: 80C51 ; ; Description: ; ; This program generates a differential in-phase (sine) on (OUTA–OUTB) ; and it’s quadrature (cosine) as a differential signal on (OUTC–OUTD). ; ;  1998, Texas Instruments Inc.
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TLV5614 2.7-V TO 5.
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TLV5614 2.7-V TO 5.
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TLV5614 2.7-V TO 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV5614CPWR Package Package Pins Type Drawing TSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV5614IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV5614IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5614CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV5614IDR SOIC D 16 2500 367.0 367.0 38.0 TLV5614IPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.