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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004

WWW.TI.COM

D 12-Bit Voltage Output DAC

D Programmable Settling Time vs Power

Consumption

3 µs in Fast Mode

9 µs in Slow Mode

D Ultra Low Power Consumption:

900 µW Typ in Slow Mode at 3 V

2.1 mW Typ in Fast Mode at 3 V

D Differential Nonlinearity...<0.5 LSB Typ

D Compatible With TMS320 and SPI Serial

Ports

D Power-Down Mode (10 nA)

D Buffered High-Impedance Reference Input

D Voltage Output Range ... 2 Times the

Reference Input Voltage

D Monotonic Over Temperature

D Available in MSOP Package

applications

D Digital Servo Control Loops

D Digital Offset and Gain Adjustment

D Industrial Process Control

D Machine and Motion Control Devices

D Mass Storage Devices

description

The TLV5616 is a 12-bit voltage output

digital-to-analog converter (DAC) with a flexible

4-wire serial interface. The 4-wire serial interface

allows glueless interface to TMS320, SPI, QSPI,

and Microwire serial ports. The TLV5616 is

programmed with a 16-bit serial string containing

4 control and 12 data bits. Developed for a wide

range of supply voltages, the TLV5616 can

operate from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow

the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within

the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need

for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TLV5616 is designed for single supply operation from 2.7 V to 5.5 V.

The device is available in an 8-terminal SOIC package. The TLV5616C is characterized for operation from 0°C

to 70°C. The TLV5616I is characterized for operation from −40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

†

(D)

MSOP

(DGK)

PLASTIC DIP

(P)

0°C to 70°C TLV5616CD TLV5616CDGK TLV5616CP

−40°C to 85°C TLV5616ID TLV5616IDGK TLV5616IP

†

Available in tape and reel as the TLV5616CDR and the TLV5616IDR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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DIN

SCLK

OUT

REFIN

AGND

D, DGK, OR P PACKAGE

(TOP VIEW)

Summary of content (29 pages)

PAGE 1
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 D 12-Bit Voltage Output DAC D Programmable Settling Time vs Power D D D D D D Voltage Output Range . . . 2 Times the D D Consumption 3 µs in Fast Mode 9 µs in Slow Mode Ultra Low Power Consumption: 900 µW Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V Differential Nonlinearity . . . <0.
PAGE 2
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 functional block diagram _ 6 + REFIN 14 Serial Input Register 1 DIN 12 12-Bit Data Latch 2 SCLK 16 Cycle Timer 3 CS 4 FS 12 x2 7 OUT Update 2 Power-On Reset Speed/Power-Down Logic Terminal Functions TERMINAL NAME 2 NO. I/O DESCRIPTION AGND 5 Analog ground CS 3 I Chip select. Digital input used to enable and disable inputs, active low.
PAGE 3
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) static DAC specifications RL = 10 kΩ, CL = 100 pF PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 12 12 bits INL Integral nonlinearity See Note 4 ± 1.9 ±4 LSB DNL Differential nonlinearity See Note 5 ± 0.
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 operating characteristics over recommended operating free-air temperature range (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS ts(FS) Output settling time, full scale RL = 10 kΩ, See Note 11 CL = 100 pF, ts(CC) Output settling time, code to code RL = 10 kΩ, See Note 12 CL = 100 pF, SR S/N Slew rate RL = 10 kΩ, See Note 13
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ SCLK 1 2 tsu(D) DIN twH twL 3 4 5 15 16 th(D) D15 D14 D13 D12 tsu(FS-CK) D1 D0 tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(C16-FS) FS Figure 1. Timing Diagram 6 ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ WWW.TI.
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 2.004 2.002 3 V Fast Mode, SOURCE 2 5 V Slow Mode, SOURCE 4.005 VO − Output Voltage − V VO − Output Voltage − V 4.01 VDD = 3 V, Vref = 1 V, Full Scale 3 V Slow Mode, SOURCE 1.998 1.996 1.994 1.992 4 5 V Fast Mode, SOURCE 3.995 3.99 3.985 3.98 1.990 3.975 0 0.01 0.02 0.
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1 1 VDD = 5 V, Vref = 2 V, Full Scale I DD − Supply Current − mA I DD − Supply Current − mA VDD = 3 V, Vref = 1 V, Full Scale 0.8 Fast Mode 0.6 0.4 Fast Mode 0.8 0.6 0.4 Slow Mode Slow Mode 0.2 −55 −40 85 −25 0 25 40 70 TA − Free-Air Temperature − C° 0.
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale −10 TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD − Total Harmonic Distortion And Noise − dB 0 −20 −30 −−40 −50 Fast Mode −60 −70 −80 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale −10 −20 −30 −−40 −50 Slow Mode −60 −70 −80 0 5 10 30 20 50 100 0 5 f − Frequency − kHz
PAGE 10
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity Error − LSB INTEGRAL NONLINEARITY ERROR 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 0 256 515 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 Digital Code DNL − Differential Nonlinearity Error − LSB Figure 13 DIFFERENTIAL NONLINEARITY ERROR 0.3 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 −0.
PAGE 11
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION general function The TLV5616 is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer.
PAGE 12
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5616 to a TMS320, SPI, or Microwire port using only three pins.
PAGE 13
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION TLV5616 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example how to connect the TLV5616 to a TMS320C203 DSP. The serial interface of the TLV5616 is ideally suited to this configuration, using a maximum of four wires to make the necessary connections.
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION ;*************************************************************************************** ;* Main Program ;*************************************************************************************** .ps 1000h .
PAGE 15
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION TLV5616 interfaced to MCS51 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5616 to an MCS51 compatible microcontroller. The serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line.
PAGE 16
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION LJMP start ; Execution starts at address 0 on power−up.
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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION RSEG STACK DS 10h ; 16 Byte Stack! ;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− ; Main Program ;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− RSEG start: MOV MAIN SP,#STACK−1 ; first set Stack Pointer CLR MOV MOV MOV SETB SETB A SCON,A TMOD,#02H TH0,#0C8H T1 T0 ; ; ; ; ; SET
PAGE 18
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change.
PAGE 19
SLAS152D − DECEMBER 1997 − REVISED APRIL 2004 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) TLV5616IPE4 ACTIVE Package Type Package Pins Package Drawing Qty PDIP P 8 50 Eco Plan Lead/Ball Finish (2) Pb-Free (RoHS) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU N / A for Pkg Type (4) -40 to 85 TLV5616IP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5616CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5616IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5616IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5616CDR SOIC D 8 2500 367.0 367.0 35.0 TLV5616IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5616IDR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.