Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 20

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FEATURES DESCRIPTION

APPLICATIONS

D10

D11

LDAC

GND

OUT

REFIN

DW OR PW PACKAGE

(TOP VIEW)

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER

WITH POWER DOWN

• Single Supply 2.7-V to 5.5-V Operation

The TLV5619 is a 12-bit voltage output DAC with a

microprocessor and TMS320 compatible parallel

• ± 0.4 LSB Differential Nonlinearity (DNL),

interface. The 12 data bits are double buffered so that

±1.5 LSB Integral Nonlinearity (INL)

the output can be updated asynchronously using the

• 12-Bit Parallel Interface

LDAC pin. During normal operation, the device dissi-

• Compatible With TMS320 DSP

pates 8 mW at a 5-V supply and 4.3 mW at a 3-V

supply. The power consumption can be lowered to 50

• Internal Power On Reset

nW by setting the DAC to power-down mode.

• Settling Time 1 µs Typ

The output voltage is buffered by a ×2 gain rail-to-rail

• Low Power Consumption:

amplifier, which features a Class A output stage to

– 8 mW for 5-V Supply

improve stability and reduce settling time.

– 4.3 mW for 3-V Supply

• Reference Input Buffers

• Voltage Output

• Monotonic Over Temperature

• Asynchronous Update

• Battery Powered Test Instruments

• Digital Offset and Gain Adjustment

• Battery Operated/Remote Industrial Controls

• Machine and Motion Control Devices

• Cordless and Wireless Telephones

• Speech Synthesis

AVAILABLE OPTIONS

• Communication Modulators

• Arbitrary Waveform Generation

PACKAGE

SMALL

TSSOP (PW)

OUTLINE (DW)

0°C to 70°C TLV5619CDW TLV5619CPW

40°C to 85°C TLV5619IDW TLV5619IPW

40°C to 125°C TLV5619QDW —

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN FEATURES • • • • • • • • • • • Single Supply 2.7-V to 5.5-V Operation ± 0.4 LSB Differential Nonlinearity (DNL), ±1.5 LSB Integral Nonlinearity (INL) 12-Bit Parallel Interface Compatible With TMS320 DSP Internal Power On Reset Settling Time 1 µs Typ Low Power Consumption: – 8 mW for 5-V Supply – 4.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage (VDD to GND) 7V Analog input voltage range - 0.3 V to VDD + 0.3 V Reference input voltage VDD + 0.3 V Digital input voltage range to GND Operating free-air temperature range, TA - 0.3 V to VDD + 0.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, sdupply voltages, and reference voltages (unless otherwise noted) STATIC DAC SPECIFICATIONS PARAMETER EZS EG TEST CONDITIONS MIN Resolution Vref(REFIN) = 2.048 V at 5 V, 1.024 V at 3 V Integral nonlinearity (INL) Vref(REFIN) = 2.048 V at 5 V, 1.024 V at 3 V, Differential nonlinearity (DNL) TYP MAX 12 UNIT bits See (1) ±1.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 REFERENCE INPUT (REFIN) PARAMETER Vref Reference input voltage Ri Reference input resistance Ci Reference input capacitance TEST CONDITIONS See MIN (1) TYP MAX 0 UNIT VDD-1.5 V 10 Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc at -3 dB (2)) MΩ 5 pF 60 dB 1.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION D(0–11) X Data tsu(D) X th(D) CS tsu(CE-WE) twh(WE) WE tsu(WE-LD) LDAC Figure 1.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS MAXIMUM OUTPUT VOLTAGE vs LOAD MAXIMUM OUTPUT VOLTAGE vs LOAD 5 3 VDD = 5 V, Vref = 2 V, Input Code = 4095 VDD = 3 V, Vref = 1.2 V, Input Code = 4095 2.5 VO – Output Voltage – V VO – Output Voltage – V 4 3 2 2 1.5 1 1 100 k 10 k 1k 100 RL – Output Load – Ω 0.5 100 k 10 10 k 1k 100 RL – Output Load – Ω Figure 2. Figure 3.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY SNRD – Signal-To-Noise Ratio + Distortion – dB 80 VDD = 5 V 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 f – Frequency – kHz DNL - Differential Nonlinearity - LSB Figure 6. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 500 1000 1500 2000 2500 3000 3500 4095 Code INL - Integral Nonlinearity - LSB Figure 7. Differential Nonlinearity 4 3 2 1.
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TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS (continued) POWER DOWN SUPPLY CURRENT vs TIME 1 I DD – Supply Current – mA 0.1 0.01 0.001 0.0001 0.00001 0.000001 0 100 200 300 400 500 600 t – Time – ms Figure 9.
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TLV5619 SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 www.ti.com APPLICATION INFORMATION DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY Integral Nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
PAGE 11
TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 APPLICATION INFORMATION (continued) LINEARITY, OFFSET, AND GAIN ERROR SUING SINGLE END SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage.
PAGE 12
TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 APPLICATION INFORMATION (continued) PARALLEL INTERFACE The device latches data on the positive edge of WE. It must be enabled with CS low. LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC using the load feature, LDAC can be driven low after the positive WE edge.
PAGE 13
TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 APPLICATION INFORMATION (continued) TLV5619 INTERFACED TO TMS320C203 DSP Hardware Interface Figure 13 shows an example of the connection between the TLV5619 and the TMS320C203 DSP. The only other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using this configuration, the DAC address is 0x0084 within the I/O memory space of the TMS320C203.
PAGE 14
TLV5619 SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 APPLICATION INFORMATION (continued) SOFTWARE LISTING ; File: ramp.asm ; Description: This program generates a ramp. ;------------- I/O and memory mapped regs ----------.include "regs.asm" TLV5619 .equ 0084h ;------------- vectors ------------------------------.
PAGE 15
TLV5619 www.ti.com SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 APPLICATION INFORMATION (continued) out clrc ret .
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TLV5619CDWR SOIC TLV5619CPWR TLV5619IDWR TLV5619IPWR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.0 Q1 DW 20 2000 330.0 24.4 10.8 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5619CDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV5619CPWR TSSOP PW 20 2000 367.0 367.0 38.0 TLV5619IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV5619IPWR TSSOP PW 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.