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TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2.7-V to 5.5-V Single-Supply Operation

Four 8-Bit Voltage Output DACs

One-Half Power 8-Bit Voltage Output DAC

Fast Serial Interface...1 MHz Max

Simple Two-Wire Interface In Single

Buffered Mode

High-Impedance Reference Inputs For Each

DAC

Programmable for 1 or 2 Times Output

Range

Simultaneous-Update Facility In

Double-Buffered Mode

Internal Power-On Reset

Industry Temperature Range

Low Power Consumption

Half-Buffered Output

Power-Down Mode

applications

Programmable Voltage Sources

Digitally-Controlled Amplifiers/Attenuators

Cordless/Wireless Communications

Automatic Test Equipment

Portable Test Equipment

Process Monitoring and Control

Signal Synthesis

description

The TLV5621I is a quadruple 8-bit voltage output

digital-to-analog converter (DAC) with buffered

reference inputs (high impedance). The DAC

produces an output voltage that ranges between

either one or two times the reference voltages and

GND, and the DAC is monotonic. The device is

simple to use since it operates from a single

supply of 2.7 V to 5.5 V. A power-on reset function

is incorporated to provide repeatable start-up

conditions. A global hardware shut-down terminal

and the capability to shut down each individual

DAC with software are provided to minimize

power consumption.

Digital control of the TLV5621I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced

to all popular microprocessor and microcontroller devices. A TLV5621I 11-bit command word consists of

eight bits of data, two DAC select bits, and a range bit for selection between the times one or times two output

range. The TLV5621I digital inputs feature Schmitt triggers for high noise immunity. The DAC registers are

double buffered which allows a complete set of new values to be written to the device, and then under control

of the HWACT signal, all of the DAC outputs are updated simultaneously.

The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical

applications. The TLV5621I does not require external trimming. The TLV5621I is characterized for operation

from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

–40°C to 85°C TLV5621ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

REFA

REFB

REFC

REFD

DATA

CLK

HWACT

DACA

DACB

DACC

DACD

D PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (18 pages)

PAGE 1
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 D D D D D D D D D D 2.7-V to 5.5-V Single-Supply Operation Four 8-Bit Voltage Output DACs One-Half Power 8-Bit Voltage Output DAC Fast Serial Interface . . .
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TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 functional block diagram REFA + – DAC 8 REFB REFC REFD Latch Latch 8 8 Latch Latch 8 8 Latch Latch 8 8 Latch Latch 8 + – DAC + – DAC + – DAC CLK DATA EN HWACT ×2 + – DACA ×2 + – DACB ×2 + – DACC ×2 + – DACD Power-On Reset Serial Interface Terminal Functions TERMINAL NAME CLK NO.
PAGE 3
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times one or times two gain. On power-up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D) O + REF CODE 256 (1 ) RNG bit value) where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word. Table 1.
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DATA DAC EN (Tied High) RS RNG RNG RNG RNG SIA A B C D SIB SIC SID ACT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of CLK depending on the data in the latches. Figure 1.
PAGE 5
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 double-buffered mode (MODE = 0) In this mode, data is only latched to the output of the DACs on the falling edge of the EN strobe. Therefore, all four DACs can be written to before updating their outputs. Any number of input data blocks can be written with all having the same length. Subsequent data blocks simply overwrite previous ones with the same address until EN goes low.
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A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 RNG RNG RNG RNG RS MODE A B C D SIA SIB SIC SID ACT DAC EN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NOTE A: Data is written to the output of a DAC, and the data is latched to the output on the falling edge of EN. A control word then selects double-buffered mode. When the range is changed, the output changes on the falling edge of EN. Figure 4.
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TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 control register The control register contains ten active bits. Four bits are range select bits as on the TLC5620. The register also contains a software shutdown bit (ACT) and four shutdown inhibit bits (SIA, SIB, SIC, SID). The shutdown inhibit bits act on each DAC (DACA through DACD). The mode select bit is used to change between single and double buffered modes.
PAGE 8
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 power-on reset Power-on reset circuitry is available on the TLV5621I. The threshold to trigger a power-on reset is 1.95 V typical (1.4 V min and 2.5 V max). For a power-on reset, all DACs are shut down. The control register bit values and states after a power-on reset are listed in Table 5. Table 5.
PAGE 9
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 linearity, offset, and gain error using single-end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage.
PAGE 10
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD – GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.
PAGE 11
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 electrical characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 1.25 V, GND = 0 V, RL = 10 kΩ, CL = 100 pF, × 1 gain output range (unless otherwise noted) PARAMETER VOmax IIH(digital) IIL(digital) TEST CONDITIONS Maximum full-scale output voltage Vref = 1.
PAGE 12
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 operating characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 1.25 V, GND = 0 V, RL = 10 kΩ, CL = 100 pF, × 1 gain output range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output slew rate, rising (DACA) 0.8 V/µs Output slew rate, falling (DACA) 0.
PAGE 13
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION tw(CLK) 50% CLK 50% 50% th(DATA-CLK) tsu(DATA-CLK) DATA Figure 6. Timing of DATA Relative to CLK EN 50% 50% tw(EN) tsu(EN-CLK) tsu(CLK-EN) 50% CLK 50% DATA Figure 7. Timing of CLK Relative to EN TLV5621 DACA DACB DACC DACD 10 kΩ CL = 100 pF Figure 8.
PAGE 14
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 TYPICAL CHARACTERISTICS NEGATIVE FALL TIME AND SETTLING TIME 3 3 2.5 2.5 2 2 VO – Output Voltage – V VO – Output Voltage – V POSITIVE RISE TIME AND SETTLING TIME 1.5 1 VDD = 3 V TA = 25°C Code 00 to FF Hex Range = ×2 Vref = 1.25 V (see Notes A and B) 0.5 0 – 0.5 VDD = 3 V TA = 25°C Code FF to 00 Hex Range = ×2 Vref = 1.25 V (see Notes A and B) 1.5 1 0.5 0 – 0.
PAGE 15
TLV5621I LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.2 Range = × 2 Input Code = 255 VDD = 3 V Vref = 1.25 V I DD – Supply Current – mA 1.15 1.1 1.05 1 0.95 0.9 0.85 0.8 – 50 0 50 100 TA – Free-Air Temperature – °C Figure 13 APPLICATION INFORMATION _ TLV5621 DACA DACB DACC DACD + VO R NOTE A: Resistor R w 10 kΩ Figure 14.
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PACKAGE OPTION ADDENDUM www.ti.
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