Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 8



      

      

SLAS235B − JULY 1999 − REVISED APRIL 2004

WWW.TI.COM

features

D 8-Bit Voltage Output DAC

D Programmable Internal Reference

D Programmable Settling Time:

1 µs in Fast Mode,

3.5 µs in Slow Mode

D Compatible With TMS320 and SPI Serial

Ports

D Differential Nonlinearity...<0.2 LSB

D Monotonic Over Temperature

applications

D Digital Servo Control Loops

D Digital Offset and Gain Adjustment

D Industrial Process Control

D Machine and Motion Control Devices

D Mass Storage Devices

description

The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows

glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit

serial string containing 4 control and 8 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling

time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable

precision voltage reference, the TLV5624 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented

with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in

an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial

temperature ranges.

AVAILABLE OPTIONS

PACKAGE

SOIC

(D)

MSOP

(DGK)

0°C to 70°C TLV5624CD TLV5624CDGK

−40°C to 85°C TLV5624ID TLV5624IDGK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

  !"# $ %&'# "$  (&)*%"# +"#'

+&%#$ %! # $('%%"#$ (' #,' #'!$  '-"$ $#&!'#$

$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'

#'$#0  "** (""!'#'$

DIN

SCLK

OUT

REF

AGND

D OR DGK PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

Summary of content (23 pages)

PAGE 1
SLAS235B − JULY 1999 − REVISED APRIL 2004 D OR DGK PACKAGE (TOP VIEW) features D 8-Bit Voltage Output DAC D Programmable Internal Reference D Programmable Settling Time: D D D DIN SCLK CS FS 1 µs in Fast Mode, 3.5 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity . . . <0.
PAGE 2
SLAS235B − JULY 1999 − REVISED APRIL 2004 functional block diagram REF PGA With Output Enable Voltage Bandgap Power and Speed Control Power-On Reset 2 2 2-Bit Control Latch DIN Serial Interface and Control SCLK CS 8 8 8-Bit DAC Latch FS Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select.
PAGE 3
SLAS235B − JULY 1999 − REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SLAS235B − JULY 1999 − REVISED APRIL 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER IDD Power supply current Power down supply current PSRR Power supply rejection ratio TEST CONDITIONS TYP MAX Fast 2.3 3.3 Slow 1.5 1.9 See Figure 8 0.
PAGE 5
SLAS235B − JULY 1999 − REVISED APRIL 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 MAX VDD−1.5 Input resistance 10 Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Reference feedthrough REF = 1 Vpp at 1 kHz + 1.
PAGE 6
SLAS235B − JULY 1999 − REVISED APRIL 2004 digital input timing requirements MIN tsu(CS−FS) tsu(FS-CK) MAX UNIT 10 ns 8 ns 10 ns Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of 16th positive edge to update DAC, then setup time between FS rising edge and CS rising edge.
PAGE 7
SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 2.071 4.135 VDD = 3 V, REF = Int. 1 V, Input Code = 255 VDD = 5 V, REF = Int. 2 V, Input Code = 255 2.0705 4.134 2.0695 Output Voltage − V Output Voltage − V 2.07 Fast 2.0698 Slow 2.0685 2.068 2.0675 2.067 Fast 4.133 Slow 4.132 4.131 4.13 2.0665 2.066 0 0.5 1 1.5 2 2.
PAGE 8
SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 3 3 VDD = 5 V, REF = 2 V, Input Code = 255 VDD = 3 V, REF = 1 V, Input Code = 255 2.5 2.5 Supply Current − mA Supply Current − mA Fast Mode 2 Slow Mode 1.5 1 Fast Mode 2 1.5 Slow Mode 1 0.5 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 t − Temperature − °C 0.
PAGE 9
SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY THD − Total Harmonic Distortion − dB 0 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale −10 −20 −30 −40 −50 −60 −70 Slow Mode −80 Fast Mode −90 −100 100 10000 1000 100000 f − Frequency − Hz Figure 10 DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.
PAGE 10
SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.50 0.25 0.00 −0.25 −0.50 0 32 64 96 128 160 192 224 256 Digital Output Code Figure 12 APPLICATION INFORMATION general function The TLV5624 is an 8-bit, single supply DAC, based on a resistor string architecture.
PAGE 11
SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION serial interface (continued) TLV5624 TLV5624 CS TMS320 DSP FS DIN SCLK CS FS DIN SCLK XF0 XF1 FSX DX CLKX Figure 13. TMS320 Interface If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows an example of how to connect the TLV5624 to TMS320, SPI or Microwire using only three pins.
PAGE 12
SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION data format The 16-bit data word for the TLV5624 consists of two parts: D Program bits D New data (D15..D12) (D11..
PAGE 13
SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION Example: D Set DAC output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 2.
PAGE 14
SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5624CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5624IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5624IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5624CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5624IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5624IDR SOIC D 8 2500 367.0 367.0 35.
PAGE 19
PAGE 20
PAGE 21
PAGE 22
PAGE 23
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.