Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 8

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   

SLAS233D − JULY 1999 − REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D Dual 8-Bit Voltage Output DAC

D Programmable Internal Reference

D Programmable Settling Time

− 3 µs in Fast Mode

− 10 µs in Slow Mode

D Compatible With TMS320 and SPI Serial

Ports

D Differential Nonlinearity <0.2 LSB Max

D Monotonic Over Temperature

applications

D Digital Servo Control Loops

D Digital Offset and Gain Adjustment

D Industrial Process Control

D Machine and Motion Control Devices

D Mass Storage Devices

description

The TLV5625 is a dual 8-bit voltage output DAC

with a flexible 3-wire serial interface. The serial

interface is compatible with TMS320, SPI,

QSPI, and Microwire serial ports. It is pro-

grammed with a 16-bit serial string containing 4

control and 8 data bits.

The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a

Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC

allows the designer to optimize speed versus power dissipation.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It

is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

SOIC

(D)

0°C to 70°C TLV5625CD

−40°C to 85°C TLV5625ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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DIN

SCLK

OUTA

OUTB

REF

AGND

D PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

Summary of content (15 pages)

PAGE 1
SLAS233D − JULY 1999 − REVISED JULY 2002 features applications D Dual 8-Bit Voltage Output DAC D Programmable Internal Reference D Programmable Settling Time D D D − 3 µs in Fast Mode − 10 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity <0.
PAGE 2
SLAS233D − JULY 1999 − REVISED JULY 2002 functional block diagram REF AGND VDD Power and Speed Control Power-On Reset 2 x2 OUTA x2 OUTB DIN 8 SCLK Serial Interface and Control CS 8-Bit DAC A Latch 8 8 Buffer 8 8-Bit DAC B Latch 8 Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs.
PAGE 3
SLAS233D − JULY 1999 − REVISED JULY 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.
PAGE 4
SLAS233D − JULY 1999 − REVISED JULY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER IDD TEST CONDITIONS No load, All inputs = AGND or VDD, DAC latch = 0x800 Power supply current MIN TYP MAX Fast 1.8 2.3 Slow 0.
PAGE 5
SLAS233D − JULY 1999 − REVISED JULY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP MAX 1 UNIT µA µA −1 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS TYP MAX Fast MIN 1 3 Slow
PAGE 6
SLAS233D − JULY 1999 − REVISED JULY 2002 digital input timing requirements MIN NOM MAX UNIT tsu(CS−CK) tsu(C16-CS) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge before CS rising edge 10 ns 10 ns twH twL SCLK pulse width high 25 ns SCLK pulse width low 25 ns tsu(D) th(D) Setup time, data ready before SCLK falling edge 10 ns Hold time, data held valid after SCLK falling edg
PAGE 7
SLAS233D − JULY 1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT 3 V Slow Mode, SOURCE VO − Output Voltage − V 2.048 2.046 4.105 VDD=3 V VREF=1 V Full scale 5 V Slow Mode, SOURCE 4.100 3 V Fast Mode, SOURCE VO − Output Voltage − V 2.050 OUTPUT VOLTAGE vs LOAD CURRENT 2.044 2.042 2.040 5 V Fast Mode, SOURCE 4.090 4.085 4.080 4.075 2.038 2.036 4.095 0 −0.01 −0.02 −0.5 −0.1 −0.2 −0.5 −0.
PAGE 8
SLAS233D − JULY 1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.8 1.8 VDD=3 V VREF=1 V Full scale 1.6 Fast Mode 1.4 I DD − Supply Current − mA I DD − Supply Current − mA 1.6 1.2 1.0 0.8 Slow Mode 0.6 0.4 0.2 1.2 1.0 0.8 Slow Mode 0.6 0.4 0.2 0.0 −40 −20 0 20 40 60 80 100 0.
PAGE 9
SLAS233D − JULY 1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.10 0.08 0.06 0.04 0.02 0.00 −0.02 −0.04 −0.06 −0.08 −0.10 0 64 128 192 255 Digital Output Code Figure 10 INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.5 0.4 0.3 0.2 0.1 −0.0 −0.1 −0.2 −0.3 −0.4 −0.
PAGE 10
SLAS233D − JULY 1999 − REVISED JULY 2002 APPLICATION INFORMATION general function The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.
PAGE 11
SLAS233D − JULY 1999 − REVISED JULY 2002 APPLICATION INFORMATION data format The 16-bit data word for the TLV5625 consists of two parts: D Program bits D New data (D15..D12) (D11..
PAGE 12
SLAS233D − JULY 1999 − REVISED JULY 2002 APPLICATION INFORMATION examples of operation (continued) Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
PAGE 13
SLAS233D − JULY 1999 − REVISED JULY 2002 APPLICATION INFORMATION Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 14.
PAGE 14
SLAS233D − JULY 1999 − REVISED JULY 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°−ā 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.
PAGE 15
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