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TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

Fast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

Wide Analog Input: 0 V to AV

Differential Nonlinearity Error: < ± 0.5 LSB

Integral Nonlinearity Error: < ± 0.5 LSB

Single 2.7-V to 5.5-V Supply Operation

Low Power: 12 mW at 3 V and 35 mW at 5 V

Auto Power Down of 1 mA Max

Software Power Down: 10 µA Max

Internal OSC

Hardware Configurable

DSP and Microcontroller Compatible

Parallel Interface

Binary/Twos Complement Output

Hardware Controlled Extended Sampling

Hardware or Software Start of Conversion

applications

Mass Storage and HDD

Automotive

Digital Servos

Process Control

General-Purpose DSP

Image Sensor Processing

description

The TLV571 is an 8-bit data acquisition system

that combines a high-speed 8-bit ADC and a

parallel interface. The device contains two on-chip control registers allowing control of software conversion start

and power down via the bidirectional parallel port. The control registers can be set to a default mode using a

dummy RD

while WR is tied low allowing the registers to be hardware configurable.

The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to

and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only

12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that

automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the

ADC is further powered down to only 10 µA.

Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal

choice for high-speed digital signal processing.

AVAILABLE OPTIONS

PACKAGE

24 TSSOP

(PW)

24 SOIC

(DW)

–40°C to 85°C TLV571IPW TLV571IDW

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NC – No internal connection

CLK

DGND

INT/EOC

DGND

AIN

AGND

REFM

REFP

CSTART

A1/D7

A0/D6

DW OR PW PACKAGE

(TOP VIEW)

Summary of content (30 pages)

PAGE 1
TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 features applications D D D D D D D D D D D D D D D D D D D D Fast Throughput Rate: 1.25 MSPS at 5 V, 625 KSPS at 3 V Wide Analog Input: 0 V to AVDD Differential Nonlinearity Error: < ± 0.5 LSB Integral Nonlinearity Error: < ± 0.5 LSB Single 2.7-V to 5.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 functional block diagram REFP AVDD AIN REFM 8-BIT SAR ADC Internal Clock DVDD Three State Latch D0 – D5 D6/A0 D7/A1 MUX CLK CS RD WR CSTART Input Registers and Control Logic AGND INT/EOC DGND Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 21 AIN 23 AVDD 22 A0/D6 16 I/O Bidirectional 3-state data bus.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 detailed description analog-to-digital SAR converter Ain Charge Redistribution DAC _ SAR Register + REFM ADC Code Control Logic Figure 1 The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on Ain during the sampling period.
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TLV571 2.7 V TO 5.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 detailed description (continued) Table 1. Conversion Modes START OF CONVERSION OPERATION COMMENTS – FOR INPUT Hardware start (CSTART) CR0.D5 = 0 • • • • • Software start CR0.D5 = 1 • Repeated conversions from AIN With external clock, WR and RD rising • WR rising edge to start sampling initially.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 detailed description (continued) reference voltage input The TLV571 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 start of conversion mechanism There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start mode ADC samples for 6 clocks, then conversion occurs for ten clocks.
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t su(CSL_WRL) t h(WRH_CSH) t su(CSL_RDL) t su(CSL_RDL) CS WR t d(CSH_CSTARTL) t h(RDH_CSH) tc (10 CLKs) tc POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 t (sample) t(sample) CSTART RD t su(DAV_WRH) t h(WRH_DAV) D[0:7] Config Data t dis(RDH_DAV) ADC ADC t en(RDL_DAV) t en(RDL_DAV) INT OR EOC Auto Powerdown Figure 4. Input Conversion – Hardware CSTART, External Clock TLV571 2.7 V to 5.
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internal clock With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and conversion begins at the rising edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after each conversion.
PAGE 10
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks after sampling begins. At the end of conversion, the INT goes low telling the host that conversion is ready to be read out. EOC B low during the conversion. The external clock is active and used as the reference at all times. With this mode, WR and RD should not be applied at the rising edge of the clock (see Figure 3).
PAGE 11
software START conversion (continued) internal clock With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins at the rising edge of RD.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 software START conversion (continued) system clock source The TLV571 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used for most conversion subtasks. The source of SYSCLK is programmable via control register zero, bit 3. The source of SYSCLK is changed at the rising edge of WR of the cycle when CR0.D3 is programmed. internal clock (CR0.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 software START conversion (continued) signal-to-noise ratio + distortion (SINAD) Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 grounding and decoupling considerations General practices should apply to the PCB design to limit high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 simplified analog input analysis Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, GND to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.
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TLV571 2.7 V TO 5.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) (continued) ac specifications, AVDD = DVDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fI = 100 kHz,, 80% of FS fs = 1.
PAGE 19
TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 timing requirements, AVDD = DVDD = 5 V (unless otherwise noted) PARAMETER tc(CLK) Input In ut clock Cycle time t(sample) Reset and sampling time tc TEST CONDITIONS MIN DVDD = 4.5 V to 5.5 V 50 TYP MAX UNIT ns DVDD = 2.7 V to 3.
PAGE 20
TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS I CC – Supply Current – mA SUPPLY CURRENT vs FREE AIR TEMPERATURE 8.0 7.5 AVDD = DVDD = 5 V, 20 MHz 7.0 6.5 6.0 5.5 5.0 4.5 4.0 AVDD = DVDD = 3 V, 10 MHz 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.15 AVDD = DVDD = 3 V, External Ref = 3 V, CLK = 10 MHz, TA = 25°C 0.10 0.05 –0.00 –0.05 –0.10 –0.15 0 64 128 192 256 Digital Output Code Figure 14 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.14 0.12 0.10 0.08 0.06 0.04 0.
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TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.12 AVDD = DVDD = 5 V, External Ref = 5 V, CLK = 20 MHz, TA = 25°C 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 0 64 128 192 256 192 256 Digital Output Code Figure 16 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.
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TLV571 2.7 V TO 5.
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TLV571 2.7 V TO 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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