TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Two-Port HDMI Switch Check for Samples: TMDS261B FEATURES 1 • 2 • • • • • • • • 2:1 Sink-side switch Supporting DVI Above 1920 × 1200 and HDMI HDTV Resolutions up to 1080p With 16-Bit Color Depth Designed for Signaling Rates up to 3 Gbps Supports HDMI 1.3a Specification Adaptive Equalization on inputs to support up to 20-m HDMI Cable at 2.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com PIN FUNCTIONS PIN SIGNAL NO.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 1. Source Selection Lookup (1) CONTROL PINS (1) 6 I/O SELECTED HOT-PLUG DETECT STATUS Power Mode S2 S1 Port Selected SCL_SINK SDA_SINK H H Port 1 Terminations of port 2 are disconnected. SCL1 SDA1 HPD_SINK L Normal mode H L Port 2 Terminations of port 1 are disconnected.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 2. Control-Pin Lookup Table (1) SIGNAL LEVEL STATE H Normal mode L Low-power mode LP S[2:1] GPIO mode I2C_SEL VSadj (1) DESCRIPTION Normal operational mode for device. If LP is left floating, then a weak internal pullup to VCC pulls it to VCC. Device is forced into a low-power state, causing the inputs and outputs to go to a high-impedance state. All other inputs are ignored.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com DISSIPATION RATINGS PACKAGE PCB JEDEC STANDARD TA ≤ 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING Low-K 1066 mW 10.66 mW/°C 586 mW High-K 1481 mW 14.8 mW/°C 814 mW 64-pin TQFP (PAG) (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com DEVICE POWER The TMDS261B is designed to operate from a single 3.3-V supply voltage. The TMDS261B has three power modes of operation. These three modes are referred to as normal mode, standby mode, and low-power mode. Normal mode is designed to be used during typical operating conditions. In normal mode, the device is fully functional and consumes the greatest amount of power.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TMDS DDC and Local I2C Pins DDC I2C Buffer or Repeater: The TMDS261B provides buffering on the DDC I2C interface for each of the input ports connected. This feature isolates the capacitance on the source side from the sink side and thus helps in passing system-level compliance. See the DDC I2C Function Description section for a detailed description on how the DDC I2C buffer operates.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 5V SCL[x] SDA[x] Input 1.6 V 0.1 V tPHL2 tPLH2 5V 80% SCL_SINK SDA_SINK Output 1.6 V 20% VOL tf2 T0388-01 Figure 6. Source-Side Output AC Measurements 5V SCL_SINK SDA_SINK Input 1.6 V 0.1 V tPHL1 5V 80% SCL[x] SDA[x] Output 1.6 V 20% VOL tf1 T0389-01 Figure 7. Sink-Side Output AC Measurements 5V SCL_SINK SDA_SINK Input VOL tPLH1 5V SCL[x] SDA[x] Output 1.6 V T0390-01 Figure 8.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com SWITCHING CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 54 84 ps AVCC = 3.3 V, RT = 50 Ω, input TMDS clock frequency = 225 MHz. See Figure 14for measurement setup; residual jitter is the total jitter measured at TTP4 minus the jitter measured at TTP1. See Figure 15 for the loss profile of the cable used for tJITC(PP) measurement.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 3.3 V VID 2.8 V VID+ VID(pp) 0V VID– tPLH tPHL 80% 20% tf 80% VOD(pp) VOD 20% tr T0391-01 Figure 10. TMDS Main-Link Timing Measurements VOH VY 50% VZ VOL tsk(D) Figure 11. Definition of Intra-Pair Differential Skew VOC DVOC(SS) T0392-01 Figure 12.
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TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 50 W OS Driver 50 W + – 0 V or 3.6 V S0372-01 Figure 16. TMDS Main Link Short-Circuit Output Circuit TYPICAL CHARACTERISTICS AVCC = 3.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω PEAK-to-PEAK RESIDUAL CLOCK JITTER vs INPUT TMDS CLOCK FREQUENCY PEAK-to-PEAK RESIDUAL DATA JITTER vs INPUT TMDS DATA RATE 160 TA =25°C VCC = 3.3 V VSadj = 4.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω DIFFERENTIAL OUTPUT VOLTAGE vs RESISTANCE VOD(pp) − Differential Output Voltage − mV 1600 TA = 25°C 1400 VCC = 3.6 V 1200 1000 VCC = 3.3 V 800 VCC = 3 V 600 400 200 0 3 4 5 6 7 VSadj Resistance − kΩ G008 Figure 23. (1) The HDMI cable between TTP1 and TTP2 is 0 m (no loss) case. See Figure 15 for the loss profile of the cable.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω 780 mV 200 mV 0 –200 mV –780 mV 0 0.25 UI 0.75 UI 1.0 UI M0146-01 Figure 25. Output-Eye Mask at TTP4 Pre-emphasis Duration 120 ps 3-dB Pre-emphasis Level 80% 20% VOD p-p = 800 mV–1200 mV 20% 80% Input Signal Rise Time (20–80%) Input Signal Fall Time (20–80%) T0235-02 Figure 26.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω Figure 27. TMDS Data Rate of 250 Mbps Figure 28. TMDS Data Rate of 302.4 Mbps Figure 29. TMDS Data Rate of 360 Mbps Figure 30.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω 24 Figure 31. TMDS Data Rate of 650 Mbps Figure 32. TMDS Data Rate of 742.5 Mbps Figure 33. TMDS Data Rate of 847.5 Mbps Figure 34.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω Figure 35. TMDS Data Rate of 1350 Mbps Figure 36. TMDS Data Rate of 1485 Mbps Figure 37. TMDS Data Rate of 1856.25 Mbps Figure 38. TMDS Data Rate of 2227.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω Figure 39.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com APPLICATION INFORMATION Table 3.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com OVS T RSCL RSDA TSCL TSDA R B0344-01 2 Figure 40. I C Drivers in the TMDS261B (R Side Is the HDMI Source Side, T Side Is the HDMI Sink Side) When the T side is driven below 0.4 V by an external I2C driver, both drivers R and T are turned on. Driver R drives the R side to near 0 V, and driver T is on, but is overridden by the external I2C driver. If driver T is already on, due to a low on the R side, driver R just turns on.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Figure 43 illustrates the waveforms seen on the R-side I2C-bus when the master writes to the slave through the I2C repeater circuit of the TMDS261B. This looks like a normal I2C transmission, and the turnon and turnoff of the acknowledge signals are slightly delayed. 9th Clock Pulse - Acknowledge From Slave RSCL RSDA Figure 43.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 4. Value of k for Different Input Threshold Voltages (continued) 0.25 VDD 0.9163 0.7621 0.6286 0.5108 0.4055 0.3102 0.2231 0.1431 0.0690 0.3 VDD 0.8473 0.6931 0.5596 0.4418 0.3365 0.2412 0.1542 0.0741 — From Equation 1, Rup(min) = 5.5 V/3 mA = 1.83 kΩ to operate the bus under a 5-V pullup voltage and provide less than 3 mA when the I2C device is driving the bus to a low state.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 5V_Source (5V coming from HDMI source) VCC/5V_source VCC 1 kW 1 kW HPD_SOURCE 1 kW (internal series resistor) 10 kW HPD[1:2] HPD_SINK TMDS261B VCC HPD_SINK HPD[1:2] ON L H HPD_SOURCE L ON H L H OFF X Z H S0387-07 Figure 45. External Circuit to Drive 5-V VOH on HPD[1:2] Layout Considerations The high-speed differential TMDS inputs are the most critical paths for the TMDS261B.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com E-EDID Reading Configurations in Standby Mode When the DTV system is in standby mode, the sources do not read the E-EDID memory because the 1-kΩ pulldown resistor keeping the HPD_SINK input at logic low forces all HPD pins to output logic-low to all sources. The source does not read the E-EDID data with a low on HPD signal.
TMDS261B www.ti.com SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 A DTV Supporting an Active CEC Link In Figure 47, the CEC PHY and CEC LOGIC functions are added. The DTV can initiate and/or react to CEC signals from its remote control or other audio/video products on the same CEC bus. All sources must have their own CEC physical address to support the full functionality of the CEC link. A source reads its CEC physical address stored in its E-EDID memory after receiving a logic-high from the HPD feedback.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com SINK HPD 5V SOURCE with AC coupled HDMI output HPD 5V SDA SCL CEC SDA SCL CEC CLK D0 D1 D2 CLK D0 D1 D2 HPDx VDD (5V) VCC (3.3V) SDA SCL EQ 5V 47kW SDAx SCLx mController S1 S2 CEC LOGIC CEC E-EDID Ax1/Bx1 Ax2/Bx2 Ax3/Bx3 Ax4/Bx4 HPD_SINK 1kW CEC PHY 3.3V 4.7kW 4.7kW DDC_SDA DDC_SCL SDA_SINK SCL_SINK HDMI RX Y1/Z1 Y2/Z2 Y3/Z3 Y4/Z4 Y1/Z1 Y2/Z2 Y3/Z3 Y4/Z4 VSadj GND 4.02kW 10% Figure 47.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com SINK SOURCE in general HDMI output HPD 5V HPD 5V SDA SCL CEC SDA SCL CEC CLK D0 D1 D2 CLK D0 D1 D2 1kW 5V 47kW HPDx VDD (5V) VCC (3.3V) SDA SCL EQ SDAx SCLx mController S1 S2 CEC LOGIC CEC E-EDID Ax1/Bx1 Ax2/Bx2 Ax3/Bx3 Ax4/Bx4 HPD_SINK 1kW CEC PHY 3.3V 4.7kW 4.7kW DDC_SDA DDC_SCL SDA_SINK SCL_SINK HDMI RX Y1/Z1 Y2/Z2 Y3/Z3 Y4/Z4 Y1/Z1 Y2/Z2 Y3/Z3 Y4/Z4 VSadj GND 4.02kW 10% Figure 49.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com GENERAL I2C PROTOCOL • • • • The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 50. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA MSB Stop Acknowledge Acknowledge Slave Address Data T0396-01 2 Figure 53. I C Address, Data Cycle(s), and Stop During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so that the receiving device may drive the SDA signal low.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com A0 R/W ACK A6 SDA Not Acknowledge (Transmitter) Acknowledge Acknowledge (From Receiver) (From Transmitter) Start Condition 2 I C Device Address and Read/Write Bit D7 D0 ACK D7 D6 D1 D0 ACK Stop Condition First Data Other Last Data Byte Byte Data Bytes T0398-01 Figure 57. Multiple-Byte Read Transfer Slave Address Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Data is the register address or register data to be written Step 7 8 I2C acknowledge (slave) A Step 8 0 2 I C stop (master) P An example of the proper bit control for selecting port 2 is: Step 4: 0000 0001 Step 6: 1001 0000 EXAMPLE – READING FROM THE TMDS261B The read operation consists of two phases. The first phase is the address phase.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Step 8 7 6 5 4 3 2 1 0 I2C general address (master) 0 1 0 1 1 0 0 1 Step 9 8 I2C acknowledge (slave) A Step 10 I2C read data (slave) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Where Data is determined by the logic values contained in the internal registers. Step 11A 8 2 I C acknowledge (master) A If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Register 0x01 is read/write. Table 9. I2C Register 0x02 Lookup Table BIT VALUE STATE 7:6 Bit 7 Bit 6 1 1 1 0 Indicates port 2 is selected as the active port, all other ports are low. 0 0 Disallowed (indeterminate state, all terminations are disconnected) 0 1 Indicates standby mode: HPD[1:2] follows HPD_SINK.
TMDS261B SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Register 0x04 is read-only. Table 12. I2C Register 0x05 Lookup Table BIT VALUE STATE DEFAULT 7:0 — RSVD X DESCRIPTION Reserved. Read-only, value is indeterministic. Register 0x05 is TI internal use only. Table 13. I2C Register 0x06 Lookup Table BIT VALUE STATE DEFAULT 7:0 — RSVD X DESCRIPTION Reserved. Read-only, value is indeterministic. Register 0x06 is TI internal use only. Table 14.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TMDS261BPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS261BPAGR TQFP PAG 64 1500 367.0 367.0 45.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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