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FEATURES

APPLICATIONS

DESCRIPTION

DVD Player

STB

Digital TV

Game

Machine

TMDS

341A

TMDS341A

SLLS702B – MAY 2006 – REVISED MARCH 2007

3-TO-1 DVI/HDMI SWITCH

Exceeds 5 kV

• Compatible with HDMI 1.3a • 3.3-V Supply Operation

• Supports 2.25 Gbps Signaling Rate for 480i/p, • 80-Pin TQFP Package

720i/p, and 1080i/p Resolutions up to 12-Bit

• ROHS Compatible and 260 ° C Reflow Rated

Color Depth

• Each Port Supports HDMI or DVI Inputs

• Switching From Three Digital-Video (DVI) or

• Isolated Digital Display Control (DDC) Bus for

Digital-Audio Visual (HDMI) Sources

Unused Ports

• Digital TV

• 5-V Tolerance to all DDC and HPD_SINK

• Digital Projector

Inputs

• Audio Video Receiver

• Integrated Receiver Termination

• Inter-Pair Output Skew < 100 ps

• Intra-Pair Skew < 50 ps

• 8-dB Receiver Equalization to Compensate for

5-m DVI Cable Losses

• High Impedance Outputs When Disabled

• TMDS Inputs HBM ESD Protection

The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that

allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug

detector, and an I

C interface are supported on each port. Each TMDS channel allows signaling rates up to 2.25

Gbps.

The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from

each port are switched through a 3-to-1 multiplexer. The I

C interface of the selected input port is linked to the

C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to

HPD_SINK. For the unused ports, the I

C interfaces are isolated, and the HPD pins are kept low.

Termination resistors (50- Ω ), pulled up to V

, are integrated at each receiver input pin. External terminations

are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the

differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard

TMDS termination and OE is high, the output is high impedance.

The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize

system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation

from 0 ° C to 70 ° C.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 3-TO-1 DVI/HDMI SWITCH FEATURES • • • • • • • • • • • Compatible with HDMI 1.3a Supports 2.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM A14 B14 A13 B13 A12 B12 A11 B11 VCC (3.3 V) RINT Rx w/ EQ RINT Rx w/ EQ RINT Rx w/ EQ RINT Rx w/ EQ PRE VSADJ VCC (3.
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TMDS341A www.ti.
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TMDS341A www.ti.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 Table 1.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) –0.5 V to 4 V Anm (3), Bnm Voltage range 2.5 V to 4 V Ym, Zm, VSADJ, PRE, Sn, OE, HPDn –0.5V to 4 V SCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK –0.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ICC Supply current VIH = VCC, VIL = VCC – 0.4 V, RVSADJ = 4.64 kΩ, RT = 50 Ω, AVCC = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock PD Power dissipation VIH = VCC, VIL = VCC – 0.4 V, RVSADJ = 4.64 kΩ, RT = 50 Ω, AVCC = 3.3 V Am/Bm = 1.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION AVcc RT RT ZO = RT TMDS Driver TMDS Receiver ZO = RT Figure 1. Termination for TMDS Output Driver Vcc R R INT INT RT Y A VA TMDS Receiver VID TMDS Driver CL 0.5 pF B VB V ID VY AVcc RT Z = VA − VB Vswing = VY − VZ VZ VA VB DC Coupled Vcc AC Coupled Vcc+0.2 V Vcc−0.4 V Vcc−0.2 V 0.4 V VID V VID(pp) ID 0V −0.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) 50 W IOS TMDS Driver 50 W + _ 0 V or 3.6 V Figure 3. Short Circuit Output Current Test Circuit 1 bit 1 to N bit VODE(SS) VOD(pp) 80% 20% t PRE Figure 4. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions VOH VY 50% VZ tsk(D) VOL Figure 5.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Input−1 Kept High A B Input−2/Input−3 A Kept Low B 3.3 V VCC 2 0V S1 Clocking S2 or S3 Kept High tsx Output tsx Y 75 mV Z −75 mV Hi−Z 75 mV −75 mV 3.3 V VCC 2 0V OE tdis ten Figure 6. TMDS Outputs Control Timing Definitions VCC 2 HPD_SINK VCC 2 0.4 V HPD1 tsx(HPD) tpd(HPD) tpd(HPD) 2.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 195 230 VCC = AVCC = 3.3 V, TA = 25 C, 210 TP1 VID(PP) = 800 mVp-p, RVSADJ = 4.64 KW PRE = OE = Low Input (2:4) HDMI Data Pattern, 250 Mbps - 2.25 Gbps Input (1) Clock, 25 MHz - 165 Mhz 200 190 180 VCC = AVCC = 3.3 V, TP1 VID(PP) = 800 mV, RVSADJ = 4.64 KW Input (2:4) 2.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) RESIDUAL DETERMINISTIC JITTER vs DIFFERENTIAL INPUT VOLTAGE RESIDUAL PEAK-TO-PEAK JITTER vs DIFFERENTIAL INPUT VOLTAGE 4 9 270 Mbps 8 742.5 Mbps 7 6 1485 Mbps 5 4 3 2 1 0 VCC = AVCC = 3.3 V, TA = 25°C, -1 RVSADJ = 4.64 KW, PRE = OE = Low -2 -3 Residual Peak-Peak Jitter - % Unit Interval Residual Deterministic Jitter - % Unit Interval 10 550 750 12 11 1 0 -1 74.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) RESIDUAL PEAK-TO-PEAK JITTER (Data Channels) vs CLOCK FREQUENCY RESIDUAL PEAK-TO-PEAK JITTER (Clock Channel) vs CLOCK FREQUENCY 16 5 Channels 2, 3, 4, VCC = AVCC = 3.3 V, TA = 25°C, RVSADJ = 4.64 KW, PRE = OE = Low, Tp1 VID(PP) = 1000 mVp-p, 720p/1080i 8-Bit = 742.5 Mbps, 720p/1080i 12-Bit = 1113.75 Mbps, 1080p 8-Bit = 1485 Mbps, 1080p 12-Bit = 2227.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) HDMI Cables Running at 165-MHz Pixel Clock TP1 TP2 TP3 TMDS341A Test Board Video 28 AWG HDMI Cable TMDS 341A Format Generator Figure 20. 1-m and 5-m HDMI Cable Test Point Configuration 1-m Cable Length Eye Patterns Figure 21. Clock at TP1 Figure 22. Clock at TP2 Figure 23. Clock at TP3 Figure 24. Data at TP1 Figure 25. Data at TP2 Figure 26.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) 5-m Cable Length Eye Patterns Figure 27. Clock at TP1 Figure 28. Clock at TP2 Figure 29. Clock at TP3 Figure 30. Data at TP1 Figure 31. Data at TP2 Figure 32. Data at TP3 (DC-Coupled Input) Figure 33.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 APPLICATION INFORMATION Supply Voltage All VCC pins can be tied to a single 3.3-V power source. A 0.01-µF capacitor is connected from each VCC pin directly to ground to filter supply noise. TMDS Inputs Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input channel contains an 8-dB equalization circuit to compensate for cable losses.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 APPLICATION INFORMATION (continued) When the power source of the device, VCC, is off and the power source to termination, AVCC, is on, the output leakage current (Io(off)) specification ensures leakage current is limited to 10-µA or less. The PRE pin provides 3-dB de-emphasis, allowing output signal pre-conditioning to offset interconnect losses from the TMDS341A outputs to a TMDS receiver.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 APPLICATION INFORMATION (continued) Figure 38. Eye Diagram at Output 10-m 28-AWG Cable vs TP2 Eye Mask Figure 39. Eye Diagram Recovered by TMDS341A vs TP2 Eye Mask DDC Signal Path Observed I2C bus voltage is dependent on bus resistance, capacitance, and time. The transient bus voltage, when charging from a low state to a high state, can be calculated using equation (1).
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 APPLICATION INFORMATION (continued) Sink Switch Box Source VDDsource VDDsink Rupsource Rupsink TMDS341A SDAn Csource SDA_Sink Ccable1 CI CO Ccable2 Csink Figure 40. DDC Link from Source to Sink With External Switch Box Rupsource = 1.5-kΩ pull-up to 5 V Rupsink = 47-kΩ pull-up to 5 V Rtotal = Rupsource // Rupsink = 1.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 APPLICATION INFORMATION (continued) Table 2 summarizes the recommended cable lengths based on threshold voltages VIH = 0.7 VDD and VIL = 0.3 VDD. Table 2. Recommended Cable Lengths Under General Threshold Voltages, 0.7 VDD and 0.3 VDD, of a DDC Interface DDC THRESHOLD VOLTAGE, VIH = 0.7 VDD, VIL = 0.3 VDD SUGGESTED PULL-UP RESISTANCE (kΩ) Rupsource = 1.
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TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from A Revision (November 2006) to B Revision .......................................................................................... Page • • • • • • 24 Changed signaling rate from 1.65 Gbps to 2.25 Gbps and color depth from 8-bit to 12-bit ............................................... 1 Changed 1.65 Gbps to 2.25 Gbps ..
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PACKAGE OPTION ADDENDUM www.ti.
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MECHANICAL DATA MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 60 0,08 M 41 61 40 80 21 1 0,13 NOM 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 0,25 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4073177 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.