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STB

DigitalTV

DVDPlayer

Game

Console

TMDS351

3-to-1

PHY SX

TMDS351

www.ti.com

SLLS840B –MAY 2007– REVISED JULY 2011

2.5 Gbps 3-TO-1 DVI/HDMI SWITCH

Check for Samples: TMDS351

• 3.3-V Fixed Supply to TMDS I/Os

FEATURES

• 5-V Fixed Supply to HPD, DDC, and Source

• Compatible with HDMI 1.3a

Selection Circuits

• Supports 2.5 Gbps Signaling Rate for 480i/p,

• 64-Pin TQFP Package

720i/p, and 1080i/p Resolutions up to 12-Bit

• ROHS Compatible and 260°C Reflow Rated

Color Depth

• Integrated Receiver Termination

APPLICATIONS

• Selectable Receiver Equalization to

Accommodate to Different Input Cable

• Digital TV

Lengths

• Digital Projector

• Intra-Pair Skew < 40 ps

• Inter-Pair Skew < 65 ps

• HBM ESD Protection Exceeds 8 kV to TMDS

Inputs

DESCRIPTION

The TMDS351 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that

allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug

detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports

signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.

When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with

standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs

are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process.

Termination resistors (50-Ω), pulled up to V

, are integrated at each TMDS receiver input. External terminations

are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the

differential output voltage to be compliant with the TMDS standard.

The TMDS351 provides two levels of receiver input equalization for different ranges of cable lengths. Each

TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the

input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in

long range HDMI cables. The TMDS351 supports power saving operation. When a system is under standby

mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, V

, can be

powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits. The

HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, V

, to maintain the system

hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The

device is characterized for operation from 0°C to 70°C.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com 2.5 Gbps 3-TO-1 DVI/HDMI SWITCH Check for Samples: TMDS351 FEATURES 1 • • • • • • • Compatible with HDMI 1.3a Supports 2.5 Gbps Signaling Rate for 480i/p, 720i/p, and 1080i/p Resolutions up to 12-Bit Color Depth Integrated Receiver Termination Selectable Receiver Equalization to Accommodate to Different Input Cable Lengths Intra-Pair Skew < 40 ps Inter-Pair Skew < 65 ps HBM ESD Protection Exceeds 8 kV to TMDS Inputs • • • • 3.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com PIN FUNCTIONS PIN NAME NO.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com Table 1.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE TMDS351PAG TMDS351 64-PIN TQFP TMDS351PAGR TMDS351 64-PIN TQFP Tape/Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2) Voltage range VCC –0.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VDD Standby supply voltage TA Operating free-air temperature MIN NOM MAX 3 3.3 3.6 UNIT 4.5 5 5.5 V 0 70 °C V TMDS DIFFERENTIAL PINS VIC Input common mode voltage VCC–0.4 VCC+0.01 VID Receiver peak-to-peak differential input voltage 150 1560 mVp-p RVSADJ Resistor for TMDS compliant voltage swing range 3.66 4.02 4.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DDC I/O PINS Ilkg Input leakage current VI = 0.1 VDD to 0.9 VDD to isolated DDC inputs CIO Input/output capacitance VI(pp) = 1 V, 100 kHz RON Switch resistance IO = 3 mA, VO = 0.4 V VPASS Switch output voltage VI = 5 V, IO = 100 µA 10 µA 10 pF 40 Ω 1.9 3.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION AVcc RT RT ZO = RT TMDS Driver TMDS Receiver ZO = RT Figure 1. Termination for TMDS Output Driver Vcc R R INT INT RT Y A VA TMDS Receiver VID TMDS Driver CL 0.5 pF B VB V ID AVcc RT VY Z = VA − VB Vswing = VY − VZ VZ VA VB DC Coupled Vcc AC Coupled Vcc+0.2 V Vcc−0.4 V Vcc−0.2 V 0.4 V VID V VID(pp) ID 0V −0.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 50 W TMDS Driver IOS 50 W + _ 0 V or 3.6 V Figure 3. Short Circuit Output Current Test Circuit VOH VY 50% VZ VOL tsk(D) Figure 4.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Port 1 A B Port 2 A B Port 3 A B S1 Clocking VDD 2 VDD 0V S2 tSX tSX 75 mV Output -75 mV 75 mV Hi-Z -75 mV ten tdis Figure 6. TMDS Outputs Control Timing Definitions VDD 2 HPD_SINK VDD 2 0.4 V HPD1 tpd(HPD) tsx(HPD) tpd(HPD) 2.4 V HPD2 HPD3 0V S1 VDD 2 S2 VDD tsx(DDC) SDA_SINK 1.5V tpd(DDC) tpd(DDC) SDA1 1.5V SDA2 0V VDD SDA3 Figure 7.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SIGNAL RATE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 200 200 S1 = S2 = HIGH 150 VCC = AVCC = 3.3 V, TA = 25°C, TP1 VID(PP) = 1200 mVPP, RVSADJ = 4.02 kW, Am/Bm(2:4) HDMI Data pattern, 250 Mbps-2.5 Gbps Am/Bm(1) Clock, 25 MHz-250 MHz 100 50 S1 = HIGH S2 = LOW ICC - Supply Current - mA ICC - Supply Current - mA S1 = S2 = HIGH VCC = AVCC = 3.3 V, 150 VID(PP) = 1200 mVPP, RVSADJ = 4.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) RESIDUAL PEAK-TO-PEAK JITTER (Data Channel) vs CABLE 20 RESIDUAL PEAK-TO-PEAK JITTER (Data Channel) vs CABLE 20 See Note A See Note A Peak-to-Peak Jitter - % Tbit 16 14 12 EQ = Low 10 8 EQ = High 6 Peak-to-Peak Jitter - % Tbit 18 15 EQ = Low EQ = High 10 5 4 2 0 0 1.5m 30AWG 3m 30 AWG 5m 28AWG Cable 10m 28AWG 15m 26AWG A. 1080p 10-Bit, VCC = AVCC = 3.3 V, TA = 25°C, RVSADJ = 4.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com APPLICATION INFORMATION Supply Voltage The TMDS351 is powered up with two different power sources. One is 3.3-V VCC for the TMDS circuitry, and the other is 5-V VDD for HPD, DDC, and most of the control logic. It is recommended to provide the same 3.3-V power source to the TMDS circuitry of the TMDS351 and its output termination voltage. This minimizes the leakage current from the ESD protection circuitry.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com 0 -2 -4 spec -6 Loss -dB -8 -10 10m cable -12 -14 EQ = High -16 -18 -20 0 250 500 750 1000 1250 1500 1750 2000 f - Frequency - MHz Figure 15. Frequency Response Compensation Curve at EQ = H Internal termination circuitry which can be switched on or off, provides 50-Ω resistance to each differential input pin when a port is selected. External terminations are not required.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com HPD Pins The HPD circuits are powered by the 5-V supply. They provide 5-V TTL output signals to the SOURCE with a typical 1-kΩ output resistance. An external 1-kΩ resistor is not needed here. The HPD output of the selected source port follows the logic level of the HPD_SINK input. Unselected HPD outputs are kept low. When the device is in standby mode, all HPD outputs follow HPD_SINK.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com Layout Considerations The high-speed differential TMDS inputs are the most critical paths for the TMDS351.
PAGE 19
TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com SINK HPD 5V HPD 5V SDA SCL CEC SDA SCL CEC 5V 47kW SOURCE 1 CLK D0 CLK D0 D1 D2 D1 D2 HPD 5V HPD 5V SDA SCL CEC SDA SCL CEC CLK D0 CLK D0 D1 D2 HPD 5V SDA SCL CEC SDA SCL CEC 5V CLK D0 CLK D0 D1 D2 D1 D2 EQ mController S1 S2 SDA1 SCL1 HPD2 HPD_SINK SDA2 SCL2 SDA_SINK SCL_SINK CEC 5V 1kW 3.3V 4.7kW 4.7kW DDC_SDA DDC_SCL E-EDID A21/B21 A22/B22 A23/B23 A24/B24 47kW SOURCE 3 VCC (3.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com Case 3 – External Logic Control for HPD (See Figure 19, Port 3) When the HDMI transmitter does not have the capability of detecting the receiver termination, using the HPD signal as a reference for sensing port selections is the only possible method. External control logic for switching the connections of the HPD signals between the HPD pins of the TMDS351 and the 5-V signal from the source provides a good solution.
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TMDS351 SLLS840B – MAY 2007 – REVISED JULY 2011 www.ti.com REVISION HISTORY Changes from Original (May 2007) to Revision A Page • Changed Figure 6 ............................................................................................................................................................... 12 • Changed From: Figure 19 To: Figure 18 ............................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TMDS351PAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS351PAGR TQFP PAG 64 1500 367.0 367.0 45.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.