TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Three-Port HDMI Switch Check for Samples: TMDS361B FEATURES 1 • 2 • • • • • • • • 3:1 Sink-side switch Supporting DVI Above 1920 × 1200 and HDMI HDTV Resolutions up to 1080p With 16-Bit Color Depth Designed for Signaling Rates up to 3 Gbps Supports HDMI 1.3a Specification Adaptive Equalization on inputs to support up to 20-m HDMI Cable at 2.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com PIN FUNCTIONS PIN SIGNAL NO.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 1. Source Selection Lookup (1) CONTROL PINS 6 HOT-PLUG DETECT STATUS Power Mode S2 S1 Port Selected SCL_SINK SDA_SINK H H Port 1 Terminations of port 2 and port 3 are disconnected. SCL1 SDA1 HPD_SINK L L Normal mode H L Port 2 Terminations of port 1 and port 3 are disconnected. SCL2 SDA2 L HPD_SINK L Normal mode L L Port 3 Terminations of port 1 and port 2 are disconnected.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 2. Control-Pin Lookup Table (1) SIGNAL LEVEL STATE H Normal mode L Low-power mode LP S[2:1] GPIO mode I2C_SEL VSadj (1) DESCRIPTION Normal operational mode for device. If LP is left floating, then a weak internal pullup to VCC pulls it to VCC. Device is forced into a low-power state, causing the inputs and outputs to go to a high-impedance state. All other inputs are ignored.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com DISSIPATION RATINGS PACKAGE PCB JEDEC STANDARD TA ≤ 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING Low-K 1066 mW 10.66 mW/°C 586 mW High-K 1481 mW 14.8 mW/°C 814 mW 64-pin TQFP (PAG) (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com DEVICE POWER The TMDS361B is designed to operate from a single 3.3-V supply voltage. The TMDS361B has three power modes of operation. These three modes are referred to as normal mode, standby mode, and low-power mode. Normal mode is designed to be used during typical operating conditions. In normal mode, the device is fully functional and consumes the greatest amount of power.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TMDS DDC and Local I2C Pins DDC I2C Buffer or Repeater: The TMDS361B provides buffering on the DDC I2C interface for each of the input ports connected. This feature isolates the capacitance on the source side from the sink side and thus helps in passing system-level compliance. See the DDC I2C Function Description section for a detailed description on how the DDC I2C buffer operates.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 5V SCL[x] SDA[x] Input 1.6 V 0.1 V tPHL2 tPLH2 5V 80% SCL_SINK SDA_SINK Output 1.6 V 20% VOL tf2 T0388-01 Figure 6. Source-Side Output AC Measurements 5V SCL_SINK SDA_SINK Input 1.6 V 0.1 V tPHL1 5V 80% SCL[x] SDA[x] Output 1.6 V 20% VOL tf1 T0389-01 Figure 7. Sink-Side Output AC Measurements 5V SCL_SINK SDA_SINK Input VOL tPLH1 5V SCL[x] SDA[x] Output 1.6 V T0390-01 Figure 8.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com SWITCHING CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 54 84 ps AVCC = 3.3 V, RT = 50 Ω, input TMDS clock frequency = 225 MHz. See Figure 14for measurement setup; residual jitter is the total jitter measured at TTP4 minus the jitter measured at TTP1. See Figure 15 for the loss profile of the cable used for tJITC(PP) measurement.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 3.3 V VID 2.8 V VID+ VID(pp) 0V VID– tPLH tPHL 80% 20% tf 80% VOD(pp) VOD 20% tr T0391-01 Figure 10. TMDS Main-Link Timing Measurements VOH VY 50% VZ VOL tsk(D) Figure 11. Definition of Intra-Pair Differential Skew VOC DVOC(SS) T0392-01 Figure 12.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com 50 W OS Driver 50 W + – 0 V or 3.6 V S0372-01 Figure 16. TMDS Main Link Short-Circuit Output Circuit TYPICAL CHARACTERISTICS AVCC = 3.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω PEAK-to-PEAK RESIDUAL CLOCK JITTER vs INPUT TMDS DATA RATE PEAK-to-PEAK RESIDUAL DATA JITTER vs INPUT TMDS DATA RATE 160 TA =25°C VCC = 3.3 V VSadj = 4.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω DIFFERENTIAL OUTPUT VOLTAGE vs RESISTANCE VOD(pp) − Differential Output Voltage − mV 1600 TA = 25°C 1400 VCC = 3.6 V 1200 1000 VCC = 3.3 V 800 VCC = 3 V 600 400 200 0 3 4 5 6 7 VSadj Resistance − kΩ G008 Figure 23. (1) The HDMI cable between TTP1 and TTP2 is 0 m (no loss) case. See Figure 15 for the loss profile of the cable.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω 780 mV 200 mV 0 –200 mV –780 mV 0 0.25 UI 0.75 UI 1.0 UI M0146-01 Figure 25. Output-Eye Mask at TTP4 Pre-emphasis Duration 120 ps 3-dB Pre-emphasis Level 80% 20% VOD p-p = 800 mV–1200 mV 20% 80% Input Signal Rise Time (20–80%) Input Signal Fall Time (20–80%) T0235-02 Figure 26.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω Figure 27. TMDS Data Rate of 250 Mbps Figure 28. TMDS Data Rate of 302.4 Mbps Figure 29. TMDS Data Rate of 360 Mbps Figure 30.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω 24 Figure 31. TMDS Data Rate of 650 Mbps Figure 32. TMDS Data Rate of 742.5 Mbps Figure 33. TMDS Data Rate of 847.5 Mbps Figure 34.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω Figure 35. TMDS Data Rate of 1350 Mbps Figure 36. TMDS Data Rate of 1485 Mbps Figure 37. TMDS Data Rate of 1856.25 Mbps Figure 38. TMDS Data Rate of 2227.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50 Ω Figure 39.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com APPLICATION INFORMATION Table 3.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com OVS T RSCL RSDA TSCL TSDA R B0344-01 2 Figure 40. I C Drivers in the TMDS361B (R Side Is the HDMI Source Side, T Side Is the HDMI Sink Side) When the T side is driven below 0.4 V by an external I2C driver, both drivers R and T are turned on. Driver R drives the R side to near 0 V, and driver T is on, but is overridden by the external I2C driver. If driver T is already on due to a low on the R side, driver R just turns on.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Figure 43 illustrates the waveforms seen on the R-side I2C-bus when the master writes to the slave through the I2C repeater circuit of the TMDS361B. This looks like a normal I2C transmission, and the turnon and turnoff of the acknowledge signals are slightly delayed. 9th Clock Pulse - Acknowledge From Slave RSCL RSDA Figure 43.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 4. Value of k for Different Input Threshold Voltages Vth–\Vth+ 0.7 VDD 0.65 VDD 0.6 VDD 0.55 VDD 0.5 VDD 0.45 VDD 0.4 VDD 0.35 VDD 0.3 VDD 0.1 VDD 1.0986 0.9445 0.8109 0.6931 0.5878 0.4925 0.4055 0.3254 0.2513 0.15 VDD 1.0415 0.8873 0.7538 0.6360 0.5306 0.4353 0.3483 0.2683 0.1942 0.2 VDD 0.9808 0.8267 0.6931 0.5754 0.4700 0.3747 0.2877 0.2076 0.1335 0.25 VDD 0.9163 0.7621 0.6286 0.5108 0.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com HPD Pins The HPD circuits are powered by the 3.3-V VCC supply. This provides maximum VOH = VCC and maximum VOL= 0.4-V output signals to the SOURCE with a typical 1-kΩ output resistance. An external 1-kΩ resistor is not needed here. The HPD output of the selected source port follows the logic level of the HPD_SINK input. Unselected HPD outputs are kept low. When the device is in standby mode, all HPD outputs follow HPD_SINK.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com A DTV Supporting a Passive CEC Link In Figure 46, the DTV does not have the capability of handling CEC signals, but allows CEC signals to pass over the CEC bus. The source selection is done by the control command of the DTV. The user cannot force the command from any audio/video product on the CEC bus. The selected source reads the E-EDID data after receiving an asserted HPD signal.
TMDS361B www.ti.com SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 A DTV Supporting an Active CEC Link In Figure 47, the CEC PHY and CEC LOGIC functions are added. The DTV can initiate and/or react to CEC signals from its remote control or other audio/video products on the same CEC bus. All sources must have their own CEC physical address to support the full functionality of the CEC link. A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD feedback.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com SINK HPD 5V SOURCE 1 With AC Coupled HDMI Output HPD 5V SDA SCL CEC SDA SCL CEC CLK D0 CLK D0 D1 D2 HPD1 5V 47kW VDD (5 V) VCC (3.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com SDA SDA SCL SCL S P Start Condition Stop Condition T0393-01 2 Figure 48. I C Start and Stop Conditions GENERAL I2C PROTOCOL • • • • The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 48. All I2C-compatible devices should recognize a start condition.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition T0395-01 Figure 50. I2C Acknowledge 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA MSB Acknowledge Slave Address Stop Acknowledge Data T0396-01 Figure 51.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Acknowledge (From Receiver) Start Condition A5 A6 SDA A1 A0 R/W ACK D7 2 I C Device Address and Read/Write Bit Acknowledge (Receiver) D6 D0 ACK D1 First Data Byte Acknowledge (Receiver) D7 D6 D1 D0 ACK Stop Condition Other Last Data Byte Data Bytes T0397-01 Figure 53.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Step 2 7 6 5 4 3 2 1 0 I2C general address (master) 0 1 0 1 1 0 0 0 Step 3 8 I2C acknowledge (slave) A Step 4 7 6 5 4 3 2 1 0 I2C write sink logic address (master) 0 0 0 0 Addr Addr Addr Addr 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Step 5 8 I2C acknowledge (slave) A Step 6 2 I C write data (master) Data is the register address or register data to be written.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Step 4 7 6 5 4 3 2 1 0 I2C write sink logic address (master) 0 0 0 0 Addr Addr Addr Addr Where Addr is determined by the values shown in Table 7. Step 5 8 I2C acknowledge (slave) A Step 6 0 2 I C stop (master) P Step 6 is optional.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 8. I2C Register 0x01 Lookup Table (continued) BIT VALUE STATE 3:2 Bit 3 Bit 2 1 1 Fastest TMDS output rise- and fall-time setting + 120 ps approximately (slowest rise- and fall-time setting) 1 0 Fastest TMDS output rise- and fall-time setting + 100 ps approximately 0 1 0 0 Bit 1 Bit 0 1 0 Device enters low-power mode. 1 1 Device enters low-power mode.
TMDS361B www.ti.com SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 Register 0x03 is read/write, For disabling clock detect, value of 80h or 1000 0000b can be written to register 0x03.
TMDS361B SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011 www.ti.com Table 11. I2C Register 0x04 Lookup Table BIT VALUE STATE 7 1 Clock detected DEFAULT DESCRIPTION 0 No clock detect 6:5 X RSVD 4 0 RSVD X This bit should always read 0 3:0 0 RSVD X Reserved A valid clock signal is detected on the selected port. If clock detect is disabled in register 0x03, then bit 7 of register 0x04 is always 1. X The selected port does not have a valid clock signal.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TMDS361BPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS361BPAGR TQFP PAG 64 1500 367.0 367.0 45.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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