Datasheet

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FEATURES

APPLICATIONS

DESCRIPTION

Digital TV

TMDS

442

DVDPlayeror

DVR

Game

Machine

HighDefinitionDVD

Player

TMDS442

SLLS757A – AUGUST 2006 – REVISED MARCH 2007

www.ti.com

4-TO-2 DVI/HDMI SWITCH

• I

C Repeater Isolates Bus Capacitance at Both

Ends

• A 4-to-2 Single-Link or 2-to-1 Dual-Link

DVI/HDMI Physical Layer Switch • TMDS Inputs HBM ESD Protection Exceeds 6

• Compatible with HDMI 1.3a

• 3.3-V Supply Operation

• Supports 2.25 Gbps Signaling Rate for 480i/p,

720i/p, and 1080i/p Resolutions up to 12-Bit • 128-Pin TQFP Package

Color Depth

• ROHS Compatible and 260 ° C Reflow Rated

• Integrated Receiver Terminations

• 8-dB Receiver Equalizer Compensates for

• Digital TV

Losses From Standard HDMI Cables

• Digital Projector

• Selectable Output De-Emphasis Compensates

• Audio Video Receiver

for Losses From Flat Cables

• DVI or HDMI Switch

• High-Impedance Outputs When Disabled

The TMDS442, 4-to-2 port DVI/HDMI switch, allows up to 4 digital video interface (DVI) or high-definition

multimedia interface (HDMI) ports to be switched to two independent display blocks. The essential requirement

of picture-in-picture display from two digital audiovisual sources is having two individual DVI or HDMI receivers in

a digital display system. TMDS442 supports two DVI or HDMI receivers to enable multiple-source selection

(picture-in-picture), as well as supports acting as a 4-input 1-output video switch.

Each input or output port contains one 5-V power indicator (5V_PWR), one hot plug detector (HPD), a pair of I

interface signals (SCL/SDA), and four TMDS channels supporting data rates up to 2.25 Gbps. The 5-V power

indicator and the hot plug detector are pulled down with internal resistors, forcing a low state on these pins until

receiving a valid high signal. The I

C interface is constructed by an I

C repeater circuit to isolate the capacitance

form both ends of the buses. TMDS receivers integrate 50- Ω termination resistors pulled up to V

, which

eliminates the need for external terminations. An 8-dB input equalization cooperates to each TMDS receiver

inputs to optimize system performance through 5-meter or longer DVI or HDMI compliant cables.

TYPICAL APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (46 pages)

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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 4-TO-2 DVI/HDMI SWITCH • FEATURES 1 • A 4-to-2 Single-Link or 2-to-1 Dual-Link DVI/HDMI Physical Layer Switch • Compatible with HDMI 1.3a • Supports 2.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 A precision resistor is connected externally from the VSADJ pin to ground, for setting the differential output voltage to be compliant with the TMDS standard for all TMDS driver outputs. The PRE pin controls the TMDS output to be operated under either a standard TMDS mode or an AC de-emphasis mode.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TMDS442 www.ti.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO.
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TMDS442 www.ti.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) –0.5 V to 4 V Aim*, Bim Voltage range 2.5 V to 4 V Yjm, Zjm, , Vsadjj, HPDi, 5V_SINKj, LC_SCL, LC_SDA, LC_A0, LC_A1, GE, GPIO –0.5V to 4 V SCLi, SCL_SINKj, SDAi, SDA_SINKj, HPD_SINKj, 5V_PWRi –0.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 RECOMMENDED OPERATING CONDITIONS (continued) MIN VIL LVTTL Low-level input voltage NOM MAX UNIT GND 0.8 V CONTROL PINS (OVS) VIH LVTTL High-level input voltage 3 3.6 V VIL LVTTL Low-level input voltage -0.5 0.5 V STATUS PINS (HPD_SINK, 5V_PWR) VIH High-level input voltage 2 5.3 V VIL Low-level input voltage GND 0.8 V DDC I/O PINS (SCL_SINK, SDA_SINK) VIH High-level input voltage 0.7VCC 5.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER IIH High-level digital input current IIL Low-level digital input current TEST CONDITIONS VIH = 5.3 V MIN TYP (1) MAX UNIT -150 150 VIH = 2 V or VCC -85 85 VIL = GND or 0.8 V -20 20 µA µA STATUS PINS (HPD, 5V_SINK) VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA 2.
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TMDS442 www.ti.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TIMING CHARACTERISTICS FOR LOCAL I2C INTERFACE (LC_SCL, LC_SDA, LC_AO, LC_A1) STANDARD MODE PARAMETER MIN MAX FAST MODE MIN 100 MAX fSCL Clock frequency, SCL tw(L) Clock low period, SCL low tw(H) Clock high period, SCL high tr Rise time, SCL and SDA 1000 300 μs tf Fall time, SCL and SDA 300 300 μs tsu(1) Setup time, SDA to SCL th(1) Hold time, SCL to SDA t(buf) 4.7 400 UNIT 4 kHz μs 1.3 μs 0.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION t w(H) t w(L) tr tf SCL t su(1) t h(1) SDA A. tr and tf are measured at 20% - 80% refered to VIHmin and VILmax levels. Figure 1. SCL and SDA Timing SCL t su(2) t h(2) t su(3) t (buf) SDA Start Condition Stop Condition Figure 2. Start and Stop Conditions AVcc RT RT ZO = RT TMDS Driver ZO = RT TMDS Receiver Figure 3.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Vcc RINT RINT RT Y A TMDS Receiver VID VA TMDS Driver CL 0.5 pF VY AVcc RT Z B VZ VB VID = VA − VB Vswing = VY − VZ VA DC Coupled Vcc AC Coupled Vcc+0.2 V VB Vcc−0.4 V Vcc−0.2 V VID 0.4 V VID VID(pp) 0V −0.4 V t PHL t PLH 100% 80% Vswing VOD(O) 0V Differential VOD(pp) 20% 0% tf tr VOD(U) VOC nVOC(SS) NOTE: PRE = low.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) 1 bit VOD(PP) 1 to N bit VODE(SS) Figure 5. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions 50 W IOS TMDS Driver 50 W + _ 0 V or 3.6 V Figure 6. Short Circuit Output Current Test Circuit VOH VY 50% VZ VOL tsk(D) Figure 7.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Input-1 kept HIGH A Input-2 kept LOW A B B 3.3V Vcc 2 0V SA Clocking SB 0V kept LOW tSX Y Output tSX 75mV -75mV Z 75mV -75mV Hi-Z 3.3V Vcc 2 0V /OE tdis ten Figure 8.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Port 1 is the Source Port 2 is the Source SA Vcc 2 SB 0V 5V_PWR1 1.5V 5V 5V_PWR2 5V_PWR3 5V or 0V 5V_PWR4 5V or 0V 5V_SINK Vcc/2 tpd (5V) tsx (5V) tpd (5V) HPD_SINK 1.5V tsx (HPD) HPD1 Vcc/2 tpd (HPD) HPD2 tpd (HPD) Vcc Vcc/2 0V tpd (HPD) HPD3 0V HPD4 0V SDA1 SDA2 2.0V SDA_SINK 0.6V tsx (DDC) Figure 10.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Vcc VCC 3.3V + 10% SCL/SDA Input Vcc/2 RL=4.7kW PULSE GENERATOR 0.1V D.U.T. RT tPHL C L=100pF VIN tPLH 80% VOUT SCL_SINK/ SDA_SINK Output 80% 20% 1.5V 20% tf 3.3V + 10% tr VOL Vcc VCC 5V + 10% SCL_SINK/ SDA_SINK Input 1.5V RL=1.67kW PULSE GENERATOR 0.1V D.U.T.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 320 325 319 317 ICC - Supply Current - mA ICC - Supply Current - mA 318 VID(PP) = 1000 mV, PRE = High 316 315 VID(PP) = 1000 mV, PRE = Low 314 313 312 311 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE (AC Coupled Input: 3m Cable, Output: 1m Cable) 20 20 PRE = High, 800 mVPP 18 16 14 PRE = High, 1200 mVPP 12 10 8 6 2 See Figure 9 Jitter Test Circuit, VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) OUTPUT INTRA-PAIR SKEW vs INPUT INTRA-PAIR SKEW (DC Coupled Input: 0m, Output: 0m) 30 Output Intra-Pair Skew - ps 25 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, tr/tf > 0.3Tbit From the Source 1080p (1.485Gbps), PRE = High 20 1080i (742.5Mbps), PRE = High 15 1080i (742.5Mbps), PRE = Low 10 1080p (1.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) TP1 TP2 TP3 TP4 TMDS442 Test Board Video Format Generator HDMI Cable A TMDS 442 HDMI Cable B Eye Pattern @ TP1 @ TP2 @TP3 PRE=LOW @TP4 PRE=HIGH Cable A 1m Data Cable B 1m Clock 5m 1m Data Clock Figure 22. Eye Patterns at 148.
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TMDS442 www.ti.
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TMDS442 www.ti.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 APPLICATION INFORMATION I2C Interface Notes The I2C interface is used to access the internal registers of the TMDS442. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 24. I2C Bit Transfer Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 8 2 9 S Clock Pulse for Acknowledgement Start Condition Figure 25. I2C Acknowledge 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA Stop MSB Acknowledge Slave Address Acknowledge Data Figure 26.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 29 and Figure 30. Note that the TMDS442 does not allow multiple read transfers to occur.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 the logic levels appearing on the I2C-A1 and I2C-A0 pins. The I2C-A1 and I2C-A0 address inputs can be connected to VCC for logic 1, GND for logic 0, or can be actively driven by TTL/CMOS logic levels. The device addresses are set by the state of these pins and are not latched. Thus a dynamic address control system could be utilized to incorporate several devices on the same system.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 Table 3. TMDS442 Sink Port Register Bit Decoder (continued) BIT FUNCTION 1, 0 BIT VALUES RESULT 00 Source port 1 select 01 Source port 2 select 10 Source port 3 select 11 Source port 4 select SB SA Bits 7 (MSB), 6 and 5 – Reserved bits without function. Bit 4 – Controls the TMDS output differential voltage. Bit 3 – Controls the status of DDC interface, SCL_SINK and SDA_SINK. Bit 2 – Controls the status of TMDS interface, Y/Z.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 STEP 1 0 2 I C Start (Master) STEP 2 2 I C General Address (Master) S 7 6 5 4 3 2 1 0 0 1 0 1 1 X X 0 Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND. STEP 3 9 2 I C Acknowledge (Slave) A STEP 4 7 6 5 4 3 2 1 0 I2C Write Sink Port Address (Master) 0 0 0 0 0 0 Addr Addr Where Addr is determined by the values shown in Table 2.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND. STEP 3 9 I2C Acknowledge (Slave) A STEP 4 7 6 5 4 3 2 1 0 I2C Read Sink Port Address (Master) 0 0 0 0 0 0 Addr Addr Where Addr is determined by the values shown in Table 2.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 TMDS Outputs A 1% precision resister, 4.64-kΩ, connected from VSADJ to ground is recommended to allow the differential output swing to provide TMDS signal levels. The differential output driver provides a typical 10-mA current sink capability, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor.
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TMDS442 www.ti.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 or not connected, VOL is typically 0.5 V. When OVS is connected to GND, VOL is typically 0.65 V. When OVS is connected to VCC, VOL is typically 0.8 V. VOL is always higher than the driver R input threshold, VIL, which is typically 0.4 V, preventing lockup of the repeater loop.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 When GE sets high, or GE sets low and 5V_EN sets high, the EN signal is the AND result of the 5V_PWR and the I2CEN. When GE sets low and 5V_EN sets low, the EN signals follows the status of I2CEN. See Table 5. Table 5.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 9th Clock Pulse - Acknowledge From Slave RSCL RSDA Figure 37. Bus R Waveform Figure 38 illustrates the waveforms seen on the T-side I2C-bus under the same operation in Figure 37. On the T-side of the I2C repeater, the clock and data lines would have a positive offset from ground equal to the VOL of the driver T. After the 8th clock pulse, the data line is pulled to the VOL of the slave device which is very close to ground in this example.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 value, and C is the total load capacitance. The parameter, k, can be calculated from equation 3 by solving for t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of t. Table 6 summarizes the possible values of k under different threshold combinations. T + k RC (2) V(t) + V (1 * e *tńRC) DD (3) Table 6. Value K Upon Different Input Threshold Voltages Vth-\Vth+ 0.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 Thermal Dissipation High-K board – It is always recommended to solder the PowerPAD™ onto the thermal land. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. Thermal simulation shows the θJA of the TMDS442 is 23.2°C/W on a high-K board with a 4 x 4 thermal via array, or is 29.4°C/W under the same condition without a via array.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 PACKAGE OPTION ADDENDUM PACKAGING INFORMATION 30-August-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMDS442PNP ACTIVE HTQFP PNP 128 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS442PNPG4 ACTIVE HTQFP PNP 128 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 1.
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TMDS442 www.ti.com SLLS757A – AUGUST 2006 – REVISED MARCH 2007 Revision History Changes from Original (August 2006) to Revision A ..................................................................................................... Page • • • • • • • • • • Changed HDMI 1.3 to HDMI 1.3a.......................................................................................................................................... 1 Changed 1.65 Gbps to 2.25 Gbps and 8-Bit to 12-Bit................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TMDS442PNPR Package Package Pins Type Drawing HTQFP PNP 128 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 17.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS442PNPR HTQFP PNP 128 1000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.