Datasheet

Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressByte
(1)
StartBy
Master
ACKBy
TMP512/TMP513
From
TMP512/TMP513
NACKBy
Master
StopBy
Master
1 9 1
9
SDA
SCL
ALERT
0 0 0 1 1 0 0 R/
W 1 0 1 1 1 A1 A0
0
NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0pin.RefertoTable1.
Frame1Two-WireSlaveAddressByte
(1)
Frame2RegisterPointerByte
1
StartBy
Master
ACKBy
TMP512/TMP513
ACKBy
TMP512/TMP513
1 9 1 9
SDA
SCL
0 1 1 1 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0 Stop
¼
NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0pin.RefertoTable1.
TMP512
TMP513
SBOS491A JUNE 2010 REVISED MAY 2011
www.ti.com
Figure 26. Timing Diagram for SMBus ALERT
Figure 27. Typical Register Pointer Set
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