Datasheet

TMP512

TMP513

SBOS491A –JUNE 2010– REVISED MAY 2011

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Bit Descriptions (continued)

FC0, FC1 Fault Count Control Bits

The Fault Count Control Bits affect flags in SMBus Alert Register bits D15-D7.

Bit 3, 2 00: These flags are activated after the first conversion result with a violated limit.

01: These flags are activated after the second consecutive conversion result with a violated limit.

10: These flags are activated after the fourth consecutive conversion result with a violated limit.

11: These flags are activated after the eighth consecutive conversion result with a violated limit.

POL: Alert Polarity

Bit 1 0: Alert pin is active low.

1: Alert pin is active high.

LATCH: Alert Mode of Operation

Bit 0 0: Alert pin works in transparent mode. The SMB alert response function does not function. Alert is deasserted

when the triggering condition goes away.

1: Alert pin works in latch mode. The SMB alert response function functions when Alert pin is active. Alert will

remain asserted even if the triggering condition goes away. Alert can be deasserted by reading the Status register

(02h), using the SMBus Alert response function, resetting the part, or by disabling the alert function using the mask

bits.