Computer Hardware Algorithm Standard User's Guide
Table Of Contents
- Table of Contents
- Preface
- 1 Overview
- 2 General Programming Guidelines
- 3 Algorithm Component Model
- 3.1 Interfaces and Modules
- 3.1.1 External Identifiers
- 3.1.2 Naming Conventions
- 3.1.3 Module Initialization and Finalization
- 3.1.4 Module Instance Objects
- 3.1.5 Design-Time Object Creation
- 3.1.6 Run-Time Object Creation and Deletion
- 3.1.7 Module Configuration
- 3.1.8 Example Module
- 3.1.9 Multiple Interface Support
- 3.1.10 Interface Inheritance
- 3.1.11 Summary
- 3.2 Algorithms
- 3.3 Packaging
- 3.1 Interfaces and Modules
- 4 Algorithm Performance Characterization
- 5 DSP-Specific Guidelines
- 6 Use of the DMA Resource
- 6.1 Overview
- 6.2 Algorithm and Framework
- 6.3 Requirements for the Use of the DMA Resource
- 6.4 Logical Channel
- 6.5 Data Transfer Properties
- 6.6 Data Transfer Synchronization
- 6.7 Abstract Interface
- 6.8 Resource Characterization
- 6.9 Runtime APIs
- 6.10 Strong Ordering of DMA Transfer Requests
- 6.11 Submitting DMA Transfer Requests
- 6.12 Device Independent DMA Optimization Guideline
- 6.13 C6xxx Specific DMA Rules and Guidelines
- 6.14 C55x Specific DMA Rules and Guidelines
- 6.15 Inter-Algorithm Synchronization
- A Rules and Guidelines
- B Core Run-Time APIs
- C Bibliography
- D Glossary
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5.4.5 Interrupt Latency
5.5 TMS320C55x Rules and Guidelines
5.5.1 Stack Architecture
5.5.2 Data Models
TMS320C55x Rules and Guidelines
ST1 Field Name Use Type
INTM Interrupt mask Preserve(global)
OVM Overflow mode bit Preserve (local)
SXM Fractional mode bit Scratch (local)
XF External Flag Scratch (global)
The PMST register is used to control the processor mode and is of type Init.
PMST Field Name Use Type
AVIS Address Visibility bit Read-only (global)
CLKOFF CLKOUT disable bit Read-only (global)
DROM Map ROM into data space Read-only (local)
IPTR Interrupt Vector Table Pointer Read-only (global)
MP/MC Microprocessor/microcomputer mode bit Read-only (global)
OVLY RAM Overlay bit Read-only (local)
SMUL Saturation on multiply bit Init (local)
SST Saturation on store Init (local)
Although there are no additional rules for C54x algorithms that deal with interrupt latency, it is important to
note that all RPT and RPTZ loops are non-interruptible; i.e., once started, interrupts are blocked until the
entire loop completes. Thus, the length of these loops can have a significant effect on the worst case
interrupt latency of an algorithm.
This section describes the rules and guidelines that are specific to the TMS320C5500 family of DSPs.
The C55X CPU supports different stack configurations and the stack configuration register (4 bits) selects
the stack architecture. The selection of the stack architecture can be done only on a hardware or software
reset. To facilitate integration, each algorithm must publish the stack configuration that it uses.
Rule 31
All C55x algorithms must document the content of the stack configuration register that they follow.
Guideline 14
All C55x algorithms should not assume any specific stack configuration and should work under all the
three stack modes.
The C55X compiler supports a small memory model and a large memory model. These memory models
affect how data is placed in memory and accessed. The use of a small memory model results in code and
data sizes that are slightly smaller than when using the large memory model. However, this imposes
certain constraints on the size and memory placement. In the small memory model, the total size of the
directly accessed data in an application must all fit within a single page of memory that is 64K words in
size. Since algorithms are agnostic of where they are going to be instanced; all global and static data
references should be far references.
52 DSP-Specific Guidelines SPRU352G – June 2005 – Revised February 2007
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