Calculator User Manual
Table Of Contents
- Read This First
 - Contents
 - Figures
 - Tables
 - Examples
 - Cautions
 - Introduction
 - Architectural Overview
 - Central Processing Unit
 - Memory and I/O Spaces
 - Program Control
 - Addressing Modes
 - Assembly Language Instructions
- Instruction Set Summary
 - How To Use the Instruction Descriptions
 - Instruction Descriptions
- ABS
 - ABS
 - ADD
 - ADD
 - ADD
 - ADD
 - ADDC
 - ADDC
 - ADDS
 - ADDS
 - ADDT
 - ADDT
 - ADRK
 - AND
 - AND
 - AND
 - APAC
 - APAC
 - B
 - BACC
 - BANZ
 - BANZ
 - BCND
 - BCND
 - BIT
 - BIT
 - BITT
 - BITT
 - BLDD
 - BLDD
 - BLDD
 - BLDD
 - BLDD
 - BLPD
 - BLPD
 - BLPD
 - BLPD
 - CALA
 - CALL
 - CC
 - CC
 - CLRC
 - CLRC
 - CMPL
 - CMPR
 - DMOV
 - DMOV
 - IDLE
 - IN
 - IN
 - INTR
 - LACC
 - LACC
 - LACC
 - LACL
 - LACL
 - LACL
 - LACT
 - LACT
 - LAR
 - LAR
 - LAR
 - LDP
 - LDP
 - LPH
 - LPH
 - LST
 - LST
 - LST
 - LST
 - LT
 - LT
 - LTA
 - LTA
 - LTD
 - LTD
 - LTD
 - LTP
 - LTP
 - LTS
 - LTS
 - MAC
 - MAC
 - MAC
 - MAC
 - MACD
 - MACD
 - MACD
 - MACD
 - MACD
 - MAR
 - MAR
 - MPY
 - MPY
 - MPY
 - MPYA
 - MPYA
 - MPYS
 - MPYS
 - MPYU
 - MPYU
 - NEG
 - NEG
 - NMI
 - NOP
 - NORM
 - NORM
 - NORM
 - OR
 - OR
 - OR
 - OUT
 - OUT
 - PAC
 - POP
 - POP
 - POPD
 - POPD
 - PSHD
 - PSHD
 - PUSH
 - RET
 - RETC
 - ROL
 - ROR
 - RPT
 - RPT
 - SACH
 - SACH
 - SACL
 - SACL
 - SAR
 - SAR
 - SBRK
 - SETC
 - SETC
 - SFL
 - SFR
 - SFR
 - SPAC
 - SPH
 - SPH
 - SPL
 - SPL
 - SPLK
 - SPLK
 - SPM
 - SQRA
 - SQRA
 - SQRS
 - SQRS
 - SST
 - SST
 - SUB
 - SUB
 - SUB
 - SUB
 - SUBB
 - SUBB
 - SUBC
 - SUBC
 - SUBS
 - SUBS
 - SUBT
 - SUBT
 - TBLR
 - TBLR
 - TBLR
 - TBLW
 - TBLW
 - TBLW
 - TRAP
 - XOR
 - XOR
 - XOR
 - ZALR
 - ZALR
 
 
 - On-Chip Peripherals
 - Synchronous Serial Port
 - Asynchronous Serial Port
 - TMS320C209
 - Register Summary
 - TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
 - Program Examples
 - Submitting ROM Codes to TI
 - Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
 - E.2 Bus Protocol
 - E.3 Emulator Cable Pod
 - E.4 Emulator Cable Pod Signal Timing
 - E.5 Emulation Timing Calculations
 - E.6 Connections Between the Emulator and the Target System
 - E.7 Physical Dimensions for the 14-Pin Emulator Connector
 - E.8 Emulation Design Considerations
 
 - Glossary
 - Index
 

Index
Index-14
memory 
(continued)
introduction 4-2
local data memory
description 4-7 to 4-10
pages of (diagram) 4-7
on-chip memory, advantages 4-2
organization 4-2
overview 2-7
pins for external interfacing 4-3
program memory 4-5 to 4-6
address generation logic 5-2
address sources 5-3
RAM (dual-access)
configuration
’C203 4-33
’C204 4-36
’C209 11-8
description 2-7
RAM (single-access)
configuration 11-7
description 2-8
reset conditions 5-33
ROM
configuration
’C204 4-36
’C209 11-7
introduction 2-8
memory instructions
block move from data memory to data memory
(BLDD) 7-49
block move from program memory to data
memory (BLPD) 7-54
move data after add PREG to accumulator, load
TREG, and multiply (MACD) 7-106
move data to next higher address in data
memory (DMOV) 7-66
move data, load TREG, and add PREG to accu-
mulator (LTD) 7-95
store long immediate value to data memory
(SPLK) 7-165
table read (TBLR) 7-186
table write (TBLW) 7-189
transfer data from data memory to I/O space
(OUT) 7-132
transfer data from I/O space to data memory
(IN) 7-69
transfer word from data memory to program
memory (TBLW) 7-189
transfer word from program memory to data
memory (TBLR) 7-186
memory-mapped registers, addresses and reset
values A-2
micro stack (MSTACK) 5-6
microprocessor/microcomputer pin (MP/MC
)
definition 4-4
use in configuring memory
’C204 4-36
’C209 11-7
MINT2 bit 5-27
MINT3 bit 5-26
MODE bit 5-26
used in HOLD operation 4-27
MP/MC
 (microprocessor/microcomputer pin)
definition 4-4
use in configuring memory
’C204 4-36
’C209 11-7
MPY instruction 7-113
MPYA instruction 7-116
MPYS instruction 7-118
MPYU instruction 7-120
MSTACK (micro stack) 5-6
multicycle instructions 5-31
multiplication section of CPU 3-5
multiplier
description 3-5
introduction 2-6
multiply instructions
multiply (include load to TREG) and accumulate
previous product (MAC) 7-102
multiply (include load to TREG), accumulate pre-
vious product, and move data (MACD) 7-106
multiply (MPY) 7-113
multiply and accumulate previous product
(MPYA) 7-116
multiply and subtract previous product
(MPYS) 7-118
multiply unsigned (MPYU) 7-120
square specified value after accumulating pre-
vious product (SQRA) 7-168
square specified value after subtracting previous
product from accumulator (SQRS) 7-170
N
NEG instruction 7-122
next auxiliary register 6-11










