Calculator User Manual
Table Of Contents
- Read This First
 - Contents
 - Figures
 - Tables
 - Examples
 - Cautions
 - Introduction
 - Architectural Overview
 - Central Processing Unit
 - Memory and I/O Spaces
 - Program Control
 - Addressing Modes
 - Assembly Language Instructions
- Instruction Set Summary
 - How To Use the Instruction Descriptions
 - Instruction Descriptions
- ABS
 - ABS
 - ADD
 - ADD
 - ADD
 - ADD
 - ADDC
 - ADDC
 - ADDS
 - ADDS
 - ADDT
 - ADDT
 - ADRK
 - AND
 - AND
 - AND
 - APAC
 - APAC
 - B
 - BACC
 - BANZ
 - BANZ
 - BCND
 - BCND
 - BIT
 - BIT
 - BITT
 - BITT
 - BLDD
 - BLDD
 - BLDD
 - BLDD
 - BLDD
 - BLPD
 - BLPD
 - BLPD
 - BLPD
 - CALA
 - CALL
 - CC
 - CC
 - CLRC
 - CLRC
 - CMPL
 - CMPR
 - DMOV
 - DMOV
 - IDLE
 - IN
 - IN
 - INTR
 - LACC
 - LACC
 - LACC
 - LACL
 - LACL
 - LACL
 - LACT
 - LACT
 - LAR
 - LAR
 - LAR
 - LDP
 - LDP
 - LPH
 - LPH
 - LST
 - LST
 - LST
 - LST
 - LT
 - LT
 - LTA
 - LTA
 - LTD
 - LTD
 - LTD
 - LTP
 - LTP
 - LTS
 - LTS
 - MAC
 - MAC
 - MAC
 - MAC
 - MACD
 - MACD
 - MACD
 - MACD
 - MACD
 - MAR
 - MAR
 - MPY
 - MPY
 - MPY
 - MPYA
 - MPYA
 - MPYS
 - MPYS
 - MPYU
 - MPYU
 - NEG
 - NEG
 - NMI
 - NOP
 - NORM
 - NORM
 - NORM
 - OR
 - OR
 - OR
 - OUT
 - OUT
 - PAC
 - POP
 - POP
 - POPD
 - POPD
 - PSHD
 - PSHD
 - PUSH
 - RET
 - RETC
 - ROL
 - ROR
 - RPT
 - RPT
 - SACH
 - SACH
 - SACL
 - SACL
 - SAR
 - SAR
 - SBRK
 - SETC
 - SETC
 - SFL
 - SFR
 - SFR
 - SPAC
 - SPH
 - SPH
 - SPL
 - SPL
 - SPLK
 - SPLK
 - SPM
 - SQRA
 - SQRA
 - SQRS
 - SQRS
 - SST
 - SST
 - SUB
 - SUB
 - SUB
 - SUB
 - SUBB
 - SUBB
 - SUBC
 - SUBC
 - SUBS
 - SUBS
 - SUBT
 - SUBT
 - TBLR
 - TBLR
 - TBLR
 - TBLW
 - TBLW
 - TBLW
 - TRAP
 - XOR
 - XOR
 - XOR
 - ZALR
 - ZALR
 
 
 - On-Chip Peripherals
 - Synchronous Serial Port
 - Asynchronous Serial Port
 - TMS320C209
 - Register Summary
 - TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
 - Program Examples
 - Submitting ROM Codes to TI
 - Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
 - E.2 Bus Protocol
 - E.3 Emulator Cable Pod
 - E.4 Emulator Cable Pod Signal Timing
 - E.5 Emulation Timing Calculations
 - E.6 Connections Between the Emulator and the Target System
 - E.7 Physical Dimensions for the 14-Pin Emulator Connector
 - E.8 Emulation Design Considerations
 
 - Glossary
 - Index
 

Boot Loader
4-21
Memory and I/O Spaces
4.5.6 Boot Loader Program
*********************************************************************************
* TMS320C2xx Boot Loader Program *
* *
* This code sets up and executes boot loader code that loads program *
* code from location 8000h in external global data space and transfers it *
* to the destination address specified by the first word read from locations *
* 8000h and 8001h. *
*********************************************************************************
.length 60
GREG .set 5h ; The GREG Register
SRC .set 8000h ; Source address
DEST .set 60h ; Destination address
LENGTH .set 61h ; Code length
TEMP .set 62h ; Temporary storage
HBYTE .set 63h ; Temporary storage for upper half of 16–bit word
CODEWORD .set 64h ; Hold program code word
.sect ”bootload”
*
* Initialization
*
BOOT LDP #0 ; Set the data page to 0 (load DP with 0)
SPLK #2E00h,TEMP ; Set ARP = 1, OVM = 1, INTM = 1, DP = 0
LST #0,TEMP
SPLK #21FCh,TEMP ; Set ARB = 1, CNF = 0, SXM = 0, XF = 1, PM = 0
LST #1,TEMP
SPLK #80h,GREG ; Designate locations 8000–FFFFH as global data
; space
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* BOOT LOAD FROM 8–BIT MEMORY. MOST SIGNIFICANT BYTE IS FIRST *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*
* Determine destination address
*
ADDR LAR AR1,#SRC ; AR1 points to global address 8000h
LACC *+,8 ; Load ACC with high byte shifted left by 8 bits
SACL HBYTE ; Store high byte
LACL *+ ; Load ACC with low byte of destination
AND #0FFH ; Mask off upper 24 bits.
OR HBYTE ; OR ACC with high byte to form 16-bit
; destination address
SACL DEST ; Store destination address
*
* Determine length of code to be transferred
*
LEN LACC *+,8 ; Load ACC with high byte shifted left by 8 bits
SACL HBYTE ; Store high byte
LACL *+ ; Load ACC with low byte of length
AND #0FFH ; Mask off upper 24 bits.
OR HBYTE ; OR ACC with high byte to form 16-bit length
SACL LENGTH ; Store length
LAR AR0,LENGTH ; Load AR0 with length to be used for BANZ










