User's Manual

SPRZ153
TMS320C6201 Silicon Errata
12
4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications
EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz
Advisory 3.0.8
Revision(s) Affected: 3.0, 2.1, and 2.0
Details: A speedpath in the device causes SDCLK and SSCLK to start up 180 degrees out-of-phase
(effectively inverted) from the desired waveform. Normally, EMIF outputs are delayed 1/2 CPU
clock from the rising edge of SDCLK/SSCLK to give it adequate hold time while maintaining
more than adequate setup times.
The desired relationship is described in the TMS320C6201B data sheet (SPRS051) and is
illustrated in Figure 4 and Figure 6. However, in the case where SDCLK/SSCLK becomes
inverted (Figure 5 and Figure 7), control signals only have 1/2 CPU clock of setup to the next
SDCLK/SSCLK rising rather than 3/2 CPU clock of setup. This has two negative effects to
interface timing to external synchronous RAMs.
1. On writes, setup time to RAMs for control signals and write data is reduced by 1 CPU cycle.
Figure 4. Write Example – Desired Behavior
tohtosu
CLKOUT1 (CPU Clock)
SS/SDCLK Internal
SS/SDCLK External
Output Signals
Figure 5. Write Example – Failing Behavior
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tosu
CLKOUT1 (CPU Clock)
SS/SDCLK Internal
SS/SDCLK External
Output Signals