User's Manual

SPRZ153

TMS320C6201 Silicon Errata

EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued)

Alternate Workaround: The following alternate workarounds can help for certain board and layout configurations.

• Using faster (125 MHz or PC100) SDRAMs and/or SBSRAMs will reduce the chances

of data corruption and/or increase the frequency at which reliable memory operation

can be observed. Operation is not specified to be reliable across operating conditions

and different samples of memory and C6201B devices due to lot-to-lot variation on

both the memory and the C6201B.

• SDCLK/SSCLK can be delayed externally. This can be accomplished either via

inverter(s), precision delay device, or longer board route on the clock line. The idea is

to force the external clock to resemble the desired clock waveform as closely as

possible, providing more setup for both reads and writes.

• You may start the device at a frequency where the skew does not occur and raise the

operating frequency to the desired rate. This must be done at each processor reset.

This solution works since the speedpath exists in the reset (non-run time) operation of

the SDCLK/SSCLK circuit. Whatever operations starts at reset is observable until the

next reset.

Resolution

• Revision 3.1 of silicon will correct this problem.

CPU: L2-unit Long Instructions Corrupted During Interrupt

Advisory 3.0.9

Revision(s) Affected: 3.0, 2.1, and 2.0

Details: If an interrupt occurs causing a B-side L-unit (.L2 unit) instruction that writes a long value to be

annulled, the top 8 bits of the result will be written rather than being annulled. This bug only

applies to the B-side L-unit (.L2 unit). The A-side L-unit (.L1 unit) functions correctly. (Internal

reference number C620774)

This bug will not affect:

• Customers programming in C with no long data types.

• Customers not using code with long instructions on the .L2-unit.

• Customers only using long instructions on the .L2-unit inside loops 5 or less than

5 cycles long. (Interrupts are disabled in the five delay slots of a branch.)

Workaround: • Disable interrupts using the appropriate compiler switches or register modifications

in the affected C code.

• Disable interrupts seven execute packets before any long instructions on the .L2-unit

that are not in the delay slots of a branch.

• Use the .L1-unit for long instructions if interrupts are anticipated.

Resolution

• Revision 3.1 of silicon will correct this problem.