TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 D D D Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6202 – 4-ns Instruction Cycle Time – 250-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 2 000 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) ’C6200 CPU Core – Eight Highly Independent Functional Units: – Six ALUs (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Result) – Load-Store Architecture With 32 32-Bit General-Purpose
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) ADVANCE INFORMATION AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 GLS 384-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 2 5 4 7 6 9 8 POST OFFICE BOX 1443 11 10 12 13 15 17 19 21 14 16 18 20 22 • HOUSTON
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 description The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 functional block diagram Timers Interrupt Selector McBSPs XB Control DMA Control EMIF Control Data Memory Peripheral Bus Controller Data Memory Controller DMA Controller Expansion Bus (XB) Interface PLL ADVANCE INFORMATION CPU EMIF Power Down Program Memory Controller BootConfig.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description (continued) Program Memory 32-Bit Address 256-Bit Data Á Á External Memory Interface ADVANCE INFORMATION ÁÁÁÁ ÁÁ Á Á Á ’C62x CPU Program Fetch Control Registers Instruction Dispatch Instruction Decode Data Path A Register File A Data Path B Register File B ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ Á Á Á ÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁ Test .L1 .S1 .M1 .D1 .D2 .M2 .S2 .
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 ÁÁÁÁ Á Á ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ Á ÁÁ ÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁ ÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁ ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁ Á ÁÁ ÁÁÁÁ src1 .L1 Á ST1 Data Path A src2 dst long dst long src long src long dst dst .S1 src1 8 8 32 8 Register File A (A0–A15) src2 .M1 dst src1 src2 LD1 Á Á DA1 DA2 LD2 .
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE0 CLKMODE1† CLKMODE2† Clock/PLL Reset and Interrupts PLLV PLLG PLLF ADVANCE INFORMATION TMS TDO TDI TCK TRST EMU1 EMU0 RSV4 RSV3 RSV2 RSV1 RSV0 IEEE Standard 1149.1 (JTAG) Emulation DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status † For GLS devices only Figure 3.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description (continued) Asynchronous Memory Control 32 Data CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 TOUT1 TINP1 Memory Map Space Select 20 Synchronous Memory Control Word Address HOLD/ HOLDA Byte Enables SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE HOLD HOLDA EMIF (External Memory Interface) Timer 0 Timer 1 ADVANCE INFORMATION ED[31:0] ARE AOE AWE ARDY TOUT0 TINP0 Timers McBSP0 McBSP1
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description (continued) 32 XD[31:0] XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 XRDY Data Clocks Byte-Enable Control/ Address Control I/O Port Control XHOLD ADVANCE INFORMATION XHOLDA XFCLK XOE XRE XWE/XWAIT XCE3 XCE2 XCE1 XCE0 Arbitration Expansion Bus Host Interface Control Figure 4.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE† DESCRIPTION GJL GLS XBE3/XA5 C7 C5 XBE2/XA4 D8 A4 XBE1/XA3 A6 B5 XBE0/XA2 C8 C6 XOE A7 XRE C9 XWE/XWAIT D10 XCS A10 XAS D9 B6 I/O/Z XCNTL B10 B9 I XW/R D11 B8 I/O/Z Expansion bus host port write/read enable.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS AF26 U16 – V7 – V8 – V10 TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) CVDD – V11 – V12 – V13 – V15 – V16 A4 A1 A8 A5 A13 A12 A14 A18 A15 A22 S 1.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 development support Texas Instruments offers an extensive line of development tools for the ’C6200 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 device and development-support tool nomenclature (continued) TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = C 6202 GJL (A) –250 DEVICE SPEED RANGE –100 MHz –150 MHz –167 MHz –200 MHz –233 MHz –250 MHz –300 MHz Experimental device Prototype device Qualified device MIL-STD-883C High Rel (non-883C) DEVICE FAMILY 320 = TMS320 family TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperatu
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 documentation support (continued) The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and education.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 clock PLL All of the internal ’C6202 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. To configure the ’C6202 PLL clock for proper operation, see Figure 6 and Table 3.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Input voltage range . . . . . . . . . . .
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vref Output Under Test CT = 30 pF† IOH † Typical distributed load circuit capacitance ADVANCE INFORMATION signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 7.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN† (see Figure 8) ’C6202-200 NO. 1 tc(CLKIN) Cycle time, CLKIN 2 tw(CLKINH) 3 4 ’C6202-233 ’C6202-250 CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 MIN MIN MIN MIN MIN MIN MAX MAX MAX MAX MAX UNIT MAX 20 5 17.2 4.3 16 4 ns Pulse duration, CLKIN high 8 2.25 6.9 1.9 6.4 1.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1†‡ (see Figure 10) PARAMETER CLKMODE = x4 MIN 1 2 3 tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) UNIT CLKMODE = x1 MAX MIN MAX P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 ) + 0.5 PH – 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 ) + 0.5 PL – 0.5 PL + 0.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for XFCLK†‡ (see Figure 12) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 1 2 3 4 tc(XFCK) tw(XFCKH) Cycle time, XFCLK tw(XFCKL) tt(XFCK) MAX D * P – 0.7 D * P + 0.7 ns Pulse duration, XFCLK high (D/2) * P – 0.7 (D/2) * P + 0.7 ns Pulse duration, XFCLK low (D/2) * P – 0.7 (D/2) * P + 0.7 ns 0.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 13 – Figure 14) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 6 7 10 11 tsu(EDV-CKO1H) th(CKO1H-EDV) Setup time, read EDx valid before CLKOUT1 high tsu(ARDY-CKO1H) th(CKO1H-ARDY) UNIT MAX 4.0 ns Hold time, read EDx valid after CLKOUT1 high 0 ns Setup time, ARDY valid before CLKOUT1 high 4.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 ADVANCE INFORMATION AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 13.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 15) NO NO. ’C6202-200 ’C6202-233 ’C6202-250 MIN MIN MIN MAX MAX MAX UNIT 7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.5 2.1 2 ns 8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 1.5 1.5 1.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 Q3 9 Q4 10 SDCAS/SSADS† ADVANCE INFORMATION 11 12 SDRAS/SSOE† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 15.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 17) NO NO. 7 8 tsu(EDV-CKO2H) th(CKO2H-EDV) ’C6202-200 ’C6202-233 ’C6202-250 MIN MIN MIN MAX MAX MAX UNIT Setup time, read EDx valid before CLKOUT2 high 1 1 0.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ CLKOUT2 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 ADVANCE INFORMATION SDA10 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 17.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV CLKOUT2 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 ADVANCE INFORMATION 18 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 19.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR CLKOUT2 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS/SSOE† ADVANCE INFORMATION 9 10 SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 21.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles† (see Figure 23) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 3 toh(HOLDAL-HOLDL)Hold time, HOLD low after HOLDA low † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 RESET TIMING timing requirements for reset (see Figure 24) ’C6202-200 ’C6202-233 ’C6202-250 NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 CLKOUT2 HIGH GROUP† LOW GROUP† 11 12 XD[31:0]‡ † High group consists of: Low group consists of: Z group consists of: XFCLK IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles† (see Figure 25) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 2 3 tw(ILOW) tw(IHIGH) UNIT MAX Width of the interrupt pulse low 2P ns Width of the interrupt pulse high 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28) NO. 5 6 MIN tsu(XDV-XFCKH) th(XFCKH-XDV) Setup time, read XDx valid before XFCLK high Hold time, read XDx valid after XFCLK high MAX UNIT 2.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED) XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2]† 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT‡ 6 5 ADVANCE INFORMATION XD[31:0] D1 D2 D3 D4 † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses. Figure 27.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles† (see Figure 29–Figure 30) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 4 5 8 9 tsu(XDV-CKO1H) th(CKO1H-XDV) Setup time, read XDx valid before CLKOUT1 high tsu(XRY-CKO1H) th(CKO1H-XRY) UNIT MAX 4.0 ns Hold time, read XDx valid after CLKOUT1 high 0 ns Setup time, XRDY valid before CLKOUT1 high 4.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 2 CLKOUT1 1 1 2 3 XCEx XBE[3:0]/XA[5:2]† 5 4 XD[31:0] 6 6 XOE ADVANCE INFORMATION 7 7 XRE XWE/XWAIT‡ 9 9 8 8 XRDY§ † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING timing requirements with external device as bus master (see Figure 31 and Figure 32) 1 2 3 4 5 6 7 8 9 10 16 17 18 MIN MAX UNIT tsu(XCSV-XCKIH) th(XCKIH-XCS) Setup time, XCS valid before XCLKIN high tsu(XAS-XCKIH) th(XCKIH-XAS) Setup time, XAS valid before XCLKIN high tsu(XCTL-XCKIH) th(XCKIH-XCTL) Setup time, XCNTL valid before XCLKIN high Hold time, XCNTL valid
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R† 8 7 XW/R† XBE[3:0]/XA[5:2]‡ 10 ADVANCE INFORMATION 9 XBLAST§ 10 9 XBLAST§ 11 D1 XD[31:0] 20 13 14 12 D2 D3 15 XRDY¶ † XW/R input/output polarity selected at boot ‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R† 8 7 XW/R† 17 XBE[3:0]/XA[5:2]‡ XBE1 XBE2 XBE3 XBE4 10 9 ADVANCE INFORMATION 16 XBLAST§ 10 9 XBLAST§ 19 18 D1 XD[31:0] 20 D2 D3 15 D4 15 21 XRDY¶ † XW/R input/output polarity selected at boot ‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) timing requirements with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35) NO. 9 10 11 12 14 15 MIN MAX UNIT tsu(XDV-XCKIH) th(XCKIH-XDV) Setup time, XDx valid before XCLKIN high 4 ns Hold time, XDx valid after XCLKIN high 2.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 1 1 XAS 2 2 XW/R† XW/R† 3 3 XBLAST‡ 4 4 XBE[3:0]/XA[5:2]§ 7 6 AD XD[31:0] 8 10 D2 D1 D3 D4 11 12 ADVANCE INFORMATION 5 BE 9 XRDY 13 13 XWE/XWAIT¶ † XW/R input/output polarity selected at boot ‡ XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 1 1 XAS XW/R† 2 2 4 4 XW/R† XBLAST‡ XBE[3:0]/XA[5:2]§ 6 7 5 ADVANCE INFORMATION XD[31:0] 8 Addr D1 11 D2 12 XRDY 15 14 XBOFF XHOLD¶ XHOLDA¶ XHOLD# XHOLDA# † XW/R input/output polarity selected at boot ‡ XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING timing requirements with external device as asynchronous bus master† (see Figure 36 and Figure 37) MIN MAX UNIT 1 tw(XCSL) Pulse duration, XCS low 4P ns 2 tw(XCSH) tsu(XSEL-XCSL) Pulse duration, XCS high 3 4 10 11 12 13 4P ns Setup time, expansion bus select signals‡ valid before XCS low Hold time, expansion bus select signals‡ valid after XCS low 2 ns 2
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED) 1 10 2 10 1 XCS 3 3 4 4 XCNTL 11 11 12 12 XBE[3:0]/XA[5:2]† 3 3 4 4 XR/W‡ 3 3 4 4 XR/W‡ 13 XD[31:0] 14 13 ADVANCE INFORMATION 9 XRDY † XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ‡ XW/R input/output polarity selected at boot Figure 37.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 XHOLD/XHOLDA TIMING timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 38) NO. MIN 3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 XHOLD/XHOLDA TIMING (CONTINUED) switching characteristics for expansion bus arbitration (internal arbiter disabled)† (see Figure 39) NO. 1 PARAMETER td(XHDAH-XBLZ) td(XBHZ-XHDL) MIN Delay time, XHOLDA high to XBus low impedance‡ Delay time, XBus high impedance to XHOLD low‡ 2 † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 40) ’C6202-200 ’C6202-233 ’C6202-250 MIN 2 3 tc(CKRX) tw(CKRX) UNIT MAX Cycle time, CLKR/X CLKR/X ext 2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–1 ns 5 tsu(FRH-CKRL) (FRH CKRL) Setup time, time external FSR high before CLKR low 6 th(CKRL-FRH) h(CKRL FRH) Hold time, time external FSR high after CL
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) ADVANCE INFORMATION switching characteristics for McBSP†‡ (see Figure 40) ’C6202-200 ’C6202-233 ’C6202-250 NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 ADVANCE INFORMATION 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 40.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 41) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) 4 ns Hold time, FSR high after CLKS high 4 ns 1 2 FSR external CLKR/X (no need to resync) ADVANCE INFORMATION MAX Setup time, FSR high before CLKS high CLKS CLKR/X(needs resync) Figure 41.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 42) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) ADVANCE INFORMATION Figure 42.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 43) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 44) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 Bit 0 (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 44.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 45) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs† (see Figure 46) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 1 tw(DMACH) Pulse duration, DMAC high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. UNIT MAX 2P – 3 ns 1 DMAC[3:0] Figure 46. DMAC Timing ’C6202-200 ’C6202-233 ’C6202-250 NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs† (see Figure 48) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 1 tw(PDH) Pulse duration, PD high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. 1 PD ADVANCE INFORMATION Figure 48.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49) ’C6202-200 ’C6202-233 ’C6202-250 NO.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MECHANICAL DATA GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 25,20 SQ 24,80 25,00 TYP 1,00 16,30 NOM 0,50 AF AE AD AC AB AA Y 1,00 W U 16,30 NOM T R P N M L 0,50 ADVANCE INFORMATION V K J H G F E D C B A 1 3 2 Heat Slug 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 See Note E 3,50 MAX 1,00 NOM Seating Plane 0,70 0,50 NOTES: A. B. C. D. E. F.
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MECHANICAL DATA GLS (S-PBGA-N384) PLASTIC BALL GRID ARRAY 18,10 SQ 17,90 16,80 TYP 0,80 0,40 AB AA Y W V 0,80 U T R P N M L K G ADVANCE INFORMATION 0,40 J H F E D C B A 3 1 2 5 4 9 7 6 8 11 13 15 17 19 21 10 12 14 16 18 20 22 Heat Slug 2,80 MAX 1,00 NOM Seating Plane 0,55 0,45 0,10 M 0,15 0,45 0,35 4188959/B 12/98 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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