Memory Controller User's Guide

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2.4.2 Deactivation (DCAB and DEAC)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DCAB
DDR_A[10]
DDR_CAS
DDR_CLK
Peripheral Architecture
The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or
following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and
mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to
ensure the deactivation of all banks. Figure 5 shows the timing diagram for a DCAB command.
Figure 5. DCAB Command
14 DDR2 Memory Controller SPRUEM4A – November 2007
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