Memory Controller User's Guide

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2.4.5 Write (WRT) Command
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_CAS
DDR_DQM[3:0]
DDR_D[31:0]
DDR_A[12:0]
DDR_RAS
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
DDR_BA[2:0]
DQM7
Sample
D0 D1 D2 D3 D4 D5 D6 D7
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8
Write Latency
DDR_CLK
Peripheral Architecture
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the
WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have
a burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed.
Figure 9 shows the timing for a write on the DDR2 memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pending
commands, the DDR2 memory controller can:
• Mask out the additional data using DDR_DQM outputs
• Terminate the write burst and start a new write burst
The DDR2 memory controller does not perform the DEAC command until page information becomes
invalid.
Figure 9. DDR2 WRT Command
DDR2 Memory Controller18 SPRUEM4A – November 2007
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