Memory Controller User's Guide

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0 1 2 3 MBank 0
Row 0
Row 1
Row 2
Row N
C
o
l l
C
o
l
C
o
l
C
o
Row 0
Row N
Row 1
Row 2
CC
Bank 1
l l
0 21
oo
C C
l l
3 M
o o
Row 0
Row N
Row 1
Row 2
CC
Bank 2
l l
0 21
oo
llll
Row N
Row 2
Row 0
Row 1
Bank P 0 1 2 3 M
C C
l l
3 M
o o
o
C
o
C
o
C
o
C
Peripheral Architecture
Figure 13. DDR2 SDRAM Column, Row, and Bank Access
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
SPRUEM4A – November 2007 DDR2 Memory Controller 25
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