Memory Controller User's Guide

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DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[15:0]
DDR_DQM[2]
DDR_DQM[3]
DDR_DQS[2]
DDR_DQS[3]
DDR_D[31:16]
DDR_ZN
DDR_ZP
DDR2
memory
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR2
memory
x16−bit
LDQS
DQ[15:0]
A[12:0]
BA[2:0]
UDQS
DDR2
memory
x16−bit
UDM
LDM
CAS
RAS
WE
CS
CKE
CK
CK
200 Ω200 Ω
controller
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[15:0]
DDR_ZN
DDR_ZP
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR2
memory
x16−bit
200 Ω
200 Ω
DDR2
memory
controller
Supported Use Cases
Figure 17. Connecting DDR2 Memory Controller for 32-Bit Connection
Figure 18. Connecting DDR2 Memory Controller for 16-Bit Connection
SPRUEM4A – November 2007 DDR2 Memory Controller 37
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