Memory Controller User's Guide

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3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)
Supported Use Cases
The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2
memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in
SDTIMR and SDTIMR2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 19
and Table 20 display the register field name and corresponding DDR2 data sheet parameter name along
with the data sheet value. These tables also provide a formula to calculate the register field value and
displays the resulting calculation. Each of the equations include a minus 1 because the register fields are
defined in terms of DDR2 clock cycles minus 1. See Section 4.4 and Section 4.5 for more information.
Table 19. SDRAM Timing Register (SDTIMR) Configuration
DDR2 Data
Register Field Manual Data Manual Formula Register
Name Parameter Name Description Value (nS) (Register field must be ≥ ) Value
T_RFC t
RFC
Refresh cycle time 127.5 (t
RFC
× f
DDR2_CLK
) - 1 16
T_RP t
RP
Precharge command to 20 (t
RP
× f
DDR2_CLK
) - 1 2
refresh or activate
command
T_RCD t
RCD
Activate command to 20 (t
RCD
× f
DDR2_CLK
) - 1 2
read/write command
T_WR t
WR
Write recovery time 15 (t
WR
× f
DDR2_CLK
) - 1 1
T_RAS t
RAS
Active to precharge 45 (t
RAC
× f
DDR2_CLK
) - 1 5
command
T_RC t
RC
Activate to Activate 65 (t
RC
× f
DDR2_CLK
) - 1 8
command in the same
bank
T_RRD t
RRD
Activate to Activate 10 ((4 × t
RRD
) + (2 × t
CK
))/(4 × t
CK
) - 1 1
command in a different
bank
T_WTR t
WTR
Write to read command 10 (t
WTR
× f
DDR2_CLK
) - 1 1
delay
Note: The equation given above for the T_RRD field applies only for 8 bank DDR2 memories.
When interfacing to DDR2 memories with less than 8 banks, the T_RRD field should be
calculated using the following equation (t
RRD
× f
DDR2_CLK
) - 1.
Table 20. SDRAM Timing Register 2 (SDTIMR2) Configuration
DDR2 Data
Register Field Manual Data Manual Formula (Register Register
Name Parameter Name Description Value field must be ≥ ) Value
T_XSNR t
XSNR
Exit self refresh to a non-read 137.5 nS (t
XSNR
× f
DDR2_CLK
) - 1 18
command
T_XSRD t
XSRD
Exit self refresh to a read 200 (t
CK
cycles) t
XSRD
- 1 199
command
T_RTP t
RTP
Read to precharge command delay 7.5 nS (t
RTP
× f
DDR2_CLK
) - 1 1
T_CKE t
CKE
CKE minimum pulse width 3 (t
CK
cycles) t
CKE
- 1 2
SPRUEM4A – November 2007 DDR2 Memory Controller 39
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