Memory Controller User's Guide

List of Figures
1 Data Paths to DDR2 Memory Controller .................................................................................. 8
2 DDR2 Memory Controller Clock Block Diagram ......................................................................... 9
3 DDR2 Memory Controller Signals ........................................................................................ 11
4 Refresh Command ......................................................................................................... 13
5 DCAB Command ........................................................................................................... 14
6 DEAC Command ........................................................................................................... 15
7 ACTV Command ........................................................................................................... 16
8 DDR2 READ Command ................................................................................................... 17
9 DDR2 WRT Command .................................................................................................... 18
10 DDR2 MRS and EMRS Command ...................................................................................... 19
11 Byte Alignment (Little-Endian Mode) .................................................................................... 20
12 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 24
13 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 25
14 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 26
15 DDR2 Memory Controller Reset Block Diagram ....................................................................... 30
16 DDR2 Memory Controller Power Sleep Controller Diagram .......................................................... 34
17 Connecting DDR2 Memory Controller for 32-Bit Connection ......................................................... 37
18 Connecting DDR2 Memory Controller for 16-Bit Connection ......................................................... 37
19 SDRAM Status Register (SDRSTAT).................................................................................... 42
20 SDRAM Bank Configuration Register (SDBCR) ....................................................................... 43
21 SDRAM Refresh Control Register (SDRCR) ........................................................................... 45
22 SDRAM Timing Register (SDTIMR) ..................................................................................... 46
23 SDRAM Timing Register 2 (SDTIMR2).................................................................................. 47
24 Peripheral Bus Burst Priority Register (PBBPR) ....................................................................... 48
25 Interrupt Raw Register (IRR) ............................................................................................. 49
26 Interrupt Masked Register (IMR) ......................................................................................... 50
27 Interrupt Mask Set Register (IMSR) ..................................................................................... 51
28 Interrupt Mask Clear Register (IMCR) ................................................................................... 52
29 DDR PHY Control Register (DDRPHYCR) ............................................................................. 53
30 VTP IO Control Register (VTPIOCR) .................................................................................... 54
31 DDR VTP Register (DDRVTPR) ......................................................................................... 55
32 DDR VTP Enable Register (DDRVTPER) .............................................................................. 55
4 List of Figures SPRUEM4A – November 2007
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