Memory Controller User's Guide

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4.1 SDRAM Status Register (SDRSTAT)
DDR2 Memory Controller Registers
The SDRAM status register (SDRSTAT) is shown in Figure 19 and described in Table 25 .
Figure 19. SDRAM Status Register (SDRSTAT)
31 30 16
BE Reserved
R-x R-4000h
15 3 2 1 0
Reserved PHYRDY Reserved
R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset; -x = value is indeterminate after reset
Table 25. SDRAM Status Register (SDRSTAT) Field Descriptions
Bit Field Value Description
31 BE Big endian. Reflects the endianness mode for the device.
0 Little-endian mode
1 Big-endian mode
30-3 Reserved 0 Reserved
2 PHYRDY DDR2 memory controller DLL ready. Reflects whether the DDR2 memory controller DLL is powered up
and locked.
0 DLL is not ready, either powered down, in reset, or not locked.
1 DLL is powered up, locked, and ready for operation.
1-0 Reserved 0 Reserved
DDR2 Memory Controller42 SPRUEM4A – November 2007
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