Memory Controller User's Guide

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4.5 SDRAM Timing Register 2 (SDTIMR2)
DDR2 Memory Controller Registers
Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the
DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 register
is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. See the DDR2 data sheet for
information on the appropriate values to program each field. SDTIMR2 is shown in Figure 23 and
described in Table 29 .
Figure 23. SDRAM Timing Register 2 (SDTIMR2)
31 25 24 23 22 16
Reserved Reserved T_XSNR
R-0 R/W-x R/W-1Dh
15 8 7 5 4 0
T_XSRD T_RTP T_CKE
R/W-F1h R/W-2h R/W-5h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset; -x = value is indeterminate after reset
Table 29. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reserved
24-23 Reserved x Reserved. Reset value is indeterminate.
22-16 T_XSNR 0-7Fh Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to any other command
except a read command, minus 1. Corresponds to the t
xsnr
AC timing parameter in the DDR2 data
sheet. Calculate by:
T_XSNR = (t
xsnr
/DDR_CLK period) - 1
15-8 T_XSRD 0-FFh Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to a read command,
minus 1. Corresponds to the t
xsrd
AC timing parameter in the DDR2 data sheet. Calculate by:
T_XSRD = t
xsrd
- 1
7-5 T_RTP 0-7h Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
command, minus 1. Corresponds to the t
rtp
AC timing parameter in the DDR2 data sheet. Calculate by:
T_RTP = (t
rtp
/DDR_CLK period) - 1
4-0 T_CKE 0-1Fh Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
Corresponds to the t
cke
AC timing parameter in the DDR2 data sheet. Calculate by:
T_CKE = t
cke
- 1
SPRUEM4A – November 2007 DDR2 Memory Controller 47
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