Memory Controller User's Guide

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4.7 Interrupt Raw Register (IRR)
DDR2 Memory Controller Registers
The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs,
the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is
shown in Figure 25 and described in Table 31 .
Figure 25. Interrupt Raw Register (IRR)
31 16
Reserved
R-0
15 3 2 1 0
Reserved LT Reserved
R-0 R/W1C-0 R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); - n = value after reset
Table 31. Interrupt Raw Register (IRR) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2 LT Line trap. Write a 1 to clear LT and the LTM bit in the interrupt masked register (IMR); a write of 0 has
no effect.
0 A line trap condition has not occurred.
1 Illegal memory access type. See Section 2.14 for more details.
1-0 Reserved 0 Reserved
SPRUEM4A – November 2007 DDR2 Memory Controller 49
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