Memory Controller User's Guide

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4.10 Interrupt Mask Clear Register (IMCR)
DDR2 Memory Controller Registers
The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interrupt
is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 28 and
described in Table 34 .
Note: If the LTMCLR bit in IMCR is set concurrently with the LTMSET bit in the interrupt mask set
register (IMSR), the interrupt is not enabled and neither bit is set to 1.
Figure 28. Interrupt Mask Clear Register (IMCR)
31 16
Reserved
R-0
15 3 2 1 0
Reserved LTMCLR Reserved
R-0 R/W1C-0 R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); - n = value after reset
Table 34. Interrupt Mask Clear Register (IMCR) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2 LTMCLR Line trap interrupt clear. Write a 1 to clear LTMCLR and the LTMSET bit in the interrupt mask set
register (IMSR); a write of 0 has no effect.
0 Line trap interrupt is not enabled.
1 Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred.
1-0 Reserved 0 Reserved
52 DDR2 Memory Controller SPRUEM4A – November 2007
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